Nested JFET Gain Stages for Low-Drift Radiation-Resilient Amplifiers
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Solution Overview
Problem
JFETs are not commonly used in electronic circuits due to lower gain, manufacturing difficulties, large threshold voltage dispersion, and challenging gate voltage requirements, making them less favorable than bipolar junction transistors (BJTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs).
Innovation Solution
An all-JFET operational amplifier architecture with a single power supply rail, featuring matched JFETs and current sources, and nested gain stages to achieve equal drain currents and voltages, reducing thermal drift and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If JFETs are used in amplifiers, then radiation resilience is improved, but gain is reduced
Solution Approach 1:
The patent employs nested gain stages where inner gain stages are surrounded by outer gain stages. This nested architecture allows multiple amplification levels to be combined, achieving high overall gain while maintaining the radiation resilience of JFETs throughout the structure.
Solution Approach 2:
The amplifier is divided into multiple separate gain stages (first gain stage, second gain stage, third gain stage) rather than using a single amplification element. This segmentation allows the system to achieve high gain through cascaded stages while maintaining JFET radiation resilience in each stage.
2Reliability
If JFETs are used in amplifiers, then radiation resilience is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent uses feedback mechanisms including current mirrors and matched transistor pairs to compensate for threshold voltage variations. The feedback loops adjust operating points to maintain consistent performance despite manufacturing tolerances in JFET threshold voltages.
Solution Approach 2:
The design incorporates adjustable biasing circuits and voltage dividers that allow optimization of operating parameters. By changing bias voltages and current levels, the amplifier can be tuned to achieve optimal performance while compensating for threshold voltage dispersion in the JFETs.
3Device complexity
If conventional JFET amplifier architecture is used, then device complexity is reduced, but thermal drift increases
Solution Approach 1:
The patent implements local temperature compensation by placing matched transistor pairs and current mirrors in close thermal proximity. This ensures that components experiencing similar temperature variations maintain consistent relative characteristics, reducing thermal drift while keeping the overall architecture manageable.
Solution Approach 2:
The design uses current mirrors and matched device pairs that maintain equal potential conditions across temperature variations. By ensuring symmetric temperature exposure and matching characteristics, the circuit maintains equipotential relationships that cancel out thermal drift effects.
4Reliability
If JFETs are used in amplifiers, then radiation resilience is improved, but ease of operation deteriorates
Solution Approach 1:
The patent introduces intermediary biasing circuits, voltage dividers, and current mirrors that mediate between the power supply and the JFET gates. These intermediary circuits generate the required gate voltages automatically, eliminating the need for external multiple voltage rails and simplifying operation.
Solution Approach 2:
The amplifier design uses self-biasing configurations where the JFETs and associated circuits automatically generate their own gate voltages from the power supply. The current sources and voltage dividers create the necessary bias conditions without external intervention, making the device self-sufficient and easier to operate.
Data Source
AI summary
A junction field effect transistor (JFET) amplifier includes a first JFET gain stage having a first differential input and differential output nodes. The first JFET gain stage further includes matched first and second JFETs having gates coupled to the first differential input and terminals coupled at a common node. The first JFET gain stage also includes a current source coupled to the common node, wherein the current source includes a third JFET. The JFET amplifier further includes a second JFET gain stage having an amplifier output and a second differential input coupled to the differential output nodes.