Nested-Loop AC Coupling for Broadband Amplifier Bias Isolation
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Solution Overview
Problem
Existing broadband amplifier circuits face challenges in optimizing DC operating points for maximum efficiency and broadband performance due to parasitic effects from DC blocking capacitors, which degrade high and low frequency responses.
Innovation Solution
Implementing on-chip distributed DC blocking capacitors, high impedance converters, and nested loop circuits to minimize parasitic capacitance and adjust gain independently at high and low frequencies, using distributed capacitance and inductance to define suitable impedance and biasing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If small-valued DC blocking capacitors are added to isolate DC operating points, then high frequency operation is optimized, but parasitic capacitance degrades high frequency response
Solution Approach 1:
The patent extracts the DC blocking function from traditional capacitive elements and implements it through active circuitry (nested loop circuits with transconductance amplifiers). This removes the parasitic capacitance inherent in physical capacitors while maintaining the DC isolation function, thereby resolving the contradiction between achieving DC operating point isolation and minimizing parasitic effects that degrade high frequency response.
Solution Approach 2:
The patent replaces the passive mechanical/electrical capacitor-based DC blocking mechanism with an active electronic control system (nested loop circuits). This substitution eliminates the physical parasitic capacitance of capacitors while achieving the same DC isolation effect through active circuit control, thus improving high frequency response.
2Ease of manufacture
If on-chip DC blocking capacitors are used, then integration is improved, but capacitance value limits degrade low frequency response
Solution Approach 1:
The patent extracts the DC blocking function from physical capacitors and implements it through active nested loop circuits. This eliminates the need for on-chip capacitors entirely, achieving DC isolation through circuit topology rather than capacitive elements, thereby avoiding the low frequency response degradation caused by limited capacitance values.
Solution Approach 2:
The patent changes the fundamental parameter from capacitive reactance (1/ωC) to active circuit gain control. By using nested loop circuits with adjustable transconductance, the system achieves frequency-independent DC blocking without relying on capacitor values, thus maintaining good low frequency response while preserving on-chip integration benefits.
3Reliability
If DC operating points are decoupled to allow independent optimization, then component performance is improved, but circuit complexity increases
Solution Approach 1:
The patent employs nested loop circuits where inner loops handle specific DC operating point control functions while outer loops manage broader signal processing tasks. This hierarchical nesting allows independent optimization of each component's DC operating point while organizing the complexity in a structured manner, making the overall circuit more manageable despite the increased functionality.
Solution Approach 2:
The nested loop circuit structure serves multiple functions simultaneously: it provides DC blocking, enables independent DC operating point optimization for each component, and maintains signal processing functionality. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall circuit complexity.
Data Source
AI summary
Various embodiments of the invention provide for an AC-coupling method and systems that utilize a nested loop circuit to generate a differential mode output that facilitates an offset compensation and a common mode output that facilitates DC-biasing of an active circuit. In embodiments, the nested loop circuit comprises a differential amplifier and a differential mode loop that generates a differential mode output and a common mode loop that uses a common mode voltage and a reference voltage to generate the common mode output.