Nested-Loop Silicon ALD for Void-Free High-Aspect-Ratio Fill
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Solution Overview
Problem
Conventional semiconductor processing methods struggle to maintain the integrity of high aspect ratio features by preventing the formation of seams and voids during material deposition, leading to structural flaws in integrated circuits.
Innovation Solution
A method involving intermittent inhibition and etching operations is employed, using nitrogen-containing precursors like ammonia to form a nitrogen-containing material on the feature's upper portion, followed by silicon-containing atomic layer deposition and subsequent etching to ensure conformal fill without seams or voids, utilizing a plasma-enhanced process to control deposition and etching cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional atomic layer deposition is used to fill high aspect ratio features, then material deposition can be achieved, but seams and voids form in the deposited material
Solution Approach 1:
The deposition process is segmented into multiple cycles, each consisting of deposition followed by inhibition and/or etching. This segmentation allows controlled material placement in stages, preventing seam and void formation that occurs in single-step conventional ALD.
Solution Approach 2:
The patent employs periodic inhibition and etching operations interspersed between deposition cycles. This periodic action creates a rhythmic process where material is deposited, then selectively removed or inhibited in upper regions, repeated over multiple cycles to achieve uniform conformal fill.
2Productivity
If the aspect ratio of features increases, then device scaling is enabled, but maintaining structural integrity during processing becomes more difficult
Solution Approach 1:
The inhibition and etching operations are applied locally to the upper portions of high aspect ratio features, while the lower portions receive full deposition. This local differentiation allows the process to adapt to the specific needs of different regions within the same structure.
Solution Approach 2:
Inhibition and etching operations are performed between deposition cycles as preliminary actions to prepare the feature structure for the next deposition step, preventing structural defects before they can form.
3Productivity
If device features get smaller, then integration density increases, but controlling material formation and removal becomes more challenging
Solution Approach 1:
The process parameters for inhibition and etching are optimized to provide feedback control over material formation and removal at the nanoscale, enabling precise control even as feature sizes decrease and integration density increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables seamless and void-free gap filling of high aspect ratio features, ensuring high conformality and reducing structural defects in semiconductor devices.
Implementation Method 1
contacting the substrate with a nitrogen-containing precursor... forming plasma effluents of the nitrogen-containing precursor... form a nitrogen-containing material on an upper portion of the one or more features
Implementation Method 2
performing a silicon-containing atomic layer deposition (ALD) process... deposit a silicon-containing material in the one or more features
Implementation Method 3
The silicon-containing ALD process may be plasma-enhanced... forming plasma effluents of the nitrogen-containing precursor... forming plasma effluents of the etchant precursor
Implementation Method 4
etching a portion of the silicon-containing material from an upper portion of the one or more features... providing an etchant precursor... contacting the substrate with the etchant precursor... etch a portion of the silicon-containing material
Data Source
AI summary
Exemplary methods of semiconductor processing may include i) performing an inhibition operation on a substrate disposed within a processing region of a semiconductor processing chamber. The substrate may define one or more features characterized by an aspect ratio of greater than or about 30:1. The methods may include ii) performing a silicon-containing atomic layer deposition (ALD) process. The silicon-containing ALD process may deposit a silicon-containing material in the one or more features. The methods may include iii) etching a portion of the silicon-containing material from an upper portion of the one or more features. The methods may include iv) repeating operations i) through iii) for a plurality of cycles.