Nested Loop Execution via Implicit Predicates on Vector Processors

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Solution Overview

Problem

Existing approaches to executing nested loops on hardware accelerators result in inefficiency due to the need to fill and drain the pipeline for each iteration of the inner loop, leading to a loss of efficiency and inability to extract partial answers effectively.

Innovation Solution

Mapping nested loops onto a fixed VLIW word schedule using data validity bits and loop counters, allowing the execution of a complete nested loop on a pipelined processor without repeated pipeline filling and draining, and using predicated instructions based on iteration counts and data validity to ensure correct operation timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If nested loops are executed on a hardware accelerator with traditional pipeline approach, then the inner loop can be processed, but the pipeline must be filled and drained for each iteration causing efficiency loss

Engineering Contradiction:
Improvethroughput of nested loop executionVSAvoidtime spent on pipeline filling and draining
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The nested loop execution is segmented into distinct phases: outer loop iteration setup, inner loop processing, and result extraction. By segmenting the execution flow and using predicated instructions to conditionally execute only necessary operations in each phase, the pipeline remains full during inner loop processing without requiring repeated fill and drain cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The outer loop control operations (addressing adjustments, partial answer extraction) are performed as preliminary actions before inner loop execution and as post-actions after inner loop completion. This preliminary organization of control operations allows the pipeline to process inner loop iterations continuously without interruption, eliminating the need for repeated pipeline flushing.

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If traditional loop execution is used on hardware accelerator, then control operations can be performed, but the ability to extract partial answers efficiently is lost

Engineering Contradiction:
Improveability to extract partial answersVSAvoidnumber of iterations before returning control
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

Predicated instructions act as intermediaries between the inner loop processing and outer loop control operations. These instructions use predicate bits to conditionally enable or disable execution based on iteration count and data validity, allowing partial answers to be extracted at optimal points without disrupting the pipelined inner loop execution flow.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The execution flow is made dynamic through predicated instructions that adaptively enable or disable operations based on runtime conditions (iteration counts, data validity). This dynamic control allows the system to extract partial answers at variable points during inner loop processing, maximizing productivity while maintaining ease of operation.

Inventive Principle:
Principle #15Dynamics

3Productivity

If pipeline is flushed for each inner loop iteration, then control operations can be performed, but efficiency and throughput are reduced

Engineering Contradiction:
Improvethroughput of hardware acceleratorVSAvoidcomplexity of controlling nested loop execution
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The traditional mechanical pipeline flush mechanism is replaced with a software-based predication system. Instead of physically flushing the pipeline for each control operation, predicated instructions use bitwise operations and conditional execution to achieve the same control effect while maintaining pipeline fullness, thereby preserving throughput without sacrificing control capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS7945768B2Method and apparatus for nested instruction looping using implicit predicates
Publication Date: 2011.05.17 GOOGLE TECHNOLOGY HOLDINGS LLC
  • US7945768B2 patent drawing
  • US7945768B2 patent drawing
  • US7945768B2 patent drawing

AI summary

A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag to ‘valid’ once per outer loop iteration, as indicated by an inner counter of the input stream unit. The tag is set to ‘invalid’ in other iterations. Functional units of the vector processor operate on data values in the data path, each functional unit producing a valid result if the data validity tags associated with inputs data values are set to ‘valid’. An output stream unit of the vector processor sinks a data value from the data path once per outer loop iteration if an associated data validity tag indicates that the data value is valid.