Nested Mode Register Architecture for DDR4 Readback Access
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Solution Overview
Problem
Traditional memory devices, such as those compliant with the DDR4 standard, lack a method to directly read back data stored in mode registers, requiring extensive tuning and calibration, and have limited functionality due to a predefined number of mode registers, with one register remaining undefined.
Innovation Solution
A nested mode register architecture is introduced, accessible using the standard DDR4/LPDDR4 command protocol, allowing additional mode registers to be implemented without departing from standard specifications, enabling read access to mode register data through a modified Multipurpose Register (MPR) circuit and mode register select circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If traditional mode register architecture is used, then standard compliance is maintained, but read access to mode register data is not possible
Solution Approach 1:
The patent implements a nested mode register architecture where a first mode register is nested within a second mode register. The first mode register contains control bits that can select and enable reading of specific bits from the second mode register through the data pins. This nesting structure allows read access functionality to be added without disrupting the traditional mode register architecture, maintaining standard compliance while enabling the desired read capability.
2Adaptability or versatility
If additional mode registers are implemented, then functionality is enhanced, but standard specifications are departed from
Solution Approach 1:
The patent makes the existing mode registers multi-functional by implementing a selection mechanism. The first mode register's control bits can configure the second mode register to serve different purposes: traditional write-only operation, or readable operation where specific bits are returned through data pins. This multi-functionality allows enhanced readability and flexibility without adding new mode registers, thus maintaining standard compliance while improving adaptability.
3Loss of time
If mode register data is made readable, then tuning and calibration requirements are reduced, but access control complexity increases
Solution Approach 1:
The patent implements a self-service access control mechanism where the first mode register automatically controls access to the second mode register's data. The control bits in the first mode register enable or disable reading functionality, and the selection logic automatically routes data from the second mode register through the data pins when reading is enabled. This self-managing system reduces access control complexity compared to external control mechanisms while enabling reduced tuning and calibration time through readable mode register data.
Data Source
AI summary
Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.