Nested Multi-Chip Semiconductor Package Design
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Solution Overview
Problem
The increasing complexity of multi-chip semiconductor packages leads to higher costs due to the need for larger and more expensive leadframes and packaging techniques, such as cavity molding, which is not economically viable for smaller packages.
Innovation Solution
A semiconductor package design that reduces package size by partially stacking chips, eliminating the centrally located die pad, and using a leadframe with dual die attach pads, allowing for the less expensive mold array process (MAP) and reducing the footprint of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple chips are integrated in a traditional leadframe package, then the package can accommodate more functional components, but the package size and leadframe cost increase significantly
Solution Approach 1:
The patent implements a nested chip structure where a third chip is positioned between and partially overlapping the first and second chips. This nesting arrangement allows multiple chips to occupy a reduced footprint area on the leadframe, enabling multi-chip integration while constraining the overall package size. The third chip is disposed such that it is supported by portions of both the first and second chips, creating a compact three-dimensional arrangement.
Solution Approach 2:
The patent transitions from a traditional two-dimensional chip arrangement to a three-dimensional configuration by positioning the third chip vertically between the first and second chips. This dimensional change allows the chips to be stacked in layers rather than arranged side-by-side, significantly reducing the required leadframe area while accommodating multiple chips in the package.
2Adaptability or versatility
If traditional cavity molding is used for multi-chip packages, then the package can accommodate complex chip arrangements, but the manufacturing cost increases
Solution Approach 1:
The nested chip configuration enables the use of less expensive mold array process (MAP) technology instead of costly cavity molding. By arranging chips in a nested pattern where the third chip is supported by the first and second chips, the patent achieves complex multi-chip integration using simpler, more cost-effective manufacturing processes.
3Ease of operation
If a centrally located die pad is used to support multiple chips, then the chip arrangement is simplified, but the substrate footprint increases
Solution Approach 1:
The patent removes the traditional centrally located die pad from the substrate design. Instead of using a large central support structure, the invention allows chips to be directly mounted on the leadframe with the third chip supported by the first and second chips themselves. This extraction of the central die pad significantly reduces the substrate footprint while maintaining structural support for the multi-chip arrangement.
4Reliability
If longer bonding wires are used to connect chips to the leadframe, then the electrical connection is maintained, but the parasitic resistance increases
Solution Approach 1:
The nested chip arrangement positions the third chip between the first and second chips, creating shorter bonding wire paths for electrical connections. This compact three-dimensional configuration reduces the distance that electrical signals must travel through bonding wires, thereby reducing parasitic resistance while maintaining reliable electrical connectivity between all chips and the leadframe.
Data Source
AI summary
Semiconductor packages and method of fabricating them are described. In one embodiment, the semiconductor package includes a substrate having a first and a second die attach pad. A first die is disposed over the first die attach pad. A second die is disposed over the second die attach pad. A third die is disposed between the first and the second die. The third die having a first, a second, and a third portion such that the first portion is disposed above a portion of the first die, the second portion is disposed above a portion of the second die, and the third portion is disposed above an area between the first die and the second die.