Nested Multi-Chip Packaging With Substrate Cavities for Shorter Signal Paths
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Solution Overview
Problem
Current multi-chip packaging architectures result in larger form factors that are not suitable for all use cases, failing to meet the demands for reduced size and optimized signal integrity.
Innovation Solution
The implementation of multi-chip packaging architectures with dies attached to a base substrate and components embedded in cavities within the substrate, reducing the overall footprint and signal path length, and utilizing through substrate vias for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multi-chip integration architectures are used to increase performance, then processing capability is improved, but form factor increases
Solution Approach 1:
The patent embeds components within cavities formed in the base substrate, creating a nested structure where components are positioned inside the substrate volume rather than occupying additional planar space. This allows multiple chips and components to be integrated vertically within the footprint of a single chip, resolving the contradiction between increased processing capability and reduced form factor
Solution Approach 2:
The invention transitions from two-dimensional planar arrangement of chips to three-dimensional vertical integration by forming cavities in the base substrate and embedding components within them. This enables stacking and vertical positioning of multiple components, allowing high-density integration without increasing the package footprint
2Ease of manufacture
If components are positioned outside the die footprint, then ease of manufacturing is improved, but signal path length increases
Solution Approach 1:
Components are nested within cavities that are formed inside the base substrate footprint, allowing them to be positioned directly beneath or within the die area. This eliminates the need for external routing and minimizes signal path lengths while maintaining manufacturing simplicity through standardized cavity formation processes
Data Source
AI summary
Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.