Nested PLL Clock Generation for Low-Noise Independent Time Bases
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Solution Overview
Problem
Existing clock signal generation techniques for electronic devices, particularly in data transport networks, face challenges in achieving target phase noise specifications and efficient power consumption while generating multiple clock signals with different time bases for synchronization.
Innovation Solution
A clock product utilizing a nested phase-locked loop architecture with a single high-frequency oscillator, where a first phase-locked loop circuit generates a clock signal tracking a reference clock signal, and a second phase-locked loop circuit adjusts the divide value to oppose the first divide value adjustment, enabling the generation of multiple clock signals that satisfy target phase noise specifications without increasing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple independent clock signals are generated using separate oscillators, then each clock signal achieves independent frequency stability, but power consumption increases and device complexity increases
Solution Approach 1:
The patent combines multiple clock signal generation functions into a single oscillator system. A first phase-locked loop circuit generates a frequency-stabilized clock signal from a single oscillator, and a second phase-locked loop circuit generates a regenerated reference clock signal from the same oscillator, eliminating the need for separate oscillators and reducing power consumption while maintaining frequency stability through phase-locked loop control
Solution Approach 2:
The patent implements a nested phase-locked loop architecture where the second phase-locked loop is nested within the overall clock generation system. The second PLL takes the output of the first PLL as its input and generates a regenerated reference signal, creating a hierarchical structure that efficiently shares the main oscillator while providing independent clock outputs
2Reliability
If multiple independent clock signals are generated using separate oscillators, then each clock signal achieves independent frequency stability, but device complexity increases
Solution Approach 1:
The patent merges multiple clock generation functions into a single integrated device. Both the frequency-stabilized clock signal and the regenerated reference clock signal are generated from one oscillator through two phase-locked loop circuits, reducing the number of oscillators and associated control circuitry while maintaining frequency stability through systematic phase-locked loop control
Solution Approach 2:
The single oscillator serves multiple functions by providing the base signal for both the first phase-locked loop (generating frequency-stabilized clock) and the second phase-locked loop (generating regenerated reference clock). This multi-functional approach reduces device complexity while maintaining the reliability of multiple independent clock outputs
3Manufacturing precision
If phase noise filtering is applied to reduce phase noise in clock signals, then phase noise performance improves, but signal processing complexity increases
Solution Approach 1:
The patent employs phase-locked loop circuits that inherently provide phase noise filtering through feedback control. The phase detectors in both PLL circuits continuously monitor and correct phase deviations, automatically filtering out phase noise without requiring additional complex signal processing circuitry, thus improving phase noise performance while maintaining relatively simple device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves lower power consumption and cleaner frequency-stabilized clock signals, reducing phase noise and jitter, and effectively generates multiple clock signals compliant with SyncE and PTP standards, ensuring accurate time synchronization across networks.
Implementation Method 1
a phase-locked loop circuit including a voltage-controlled oscillator, a phase detector, a loop filter, and a frequency divider
Implementation Method 2
a phase detector coupled to the voltage-controlled oscillator and the frequency divider, the phase detector to generate a phase error signal based on a phase difference between the reference clock signal and a divided version of the clock signal
Implementation Method 3
a voltage-controlled oscillator, a phase detector, a loop filter, and a frequency divider
Data Source
AI summary
A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.