Nested PLL Clock Holdover for Multi-Frequency Source Synchronization
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Solution Overview
Problem
Existing clock holdover designs in communication systems face challenges with multiple external source clocks having different frequencies, leading to issues with non-integral multiples/fractions, which complicates circuit design and increases costs.
Innovation Solution
The integration of two phase-locked loops into a nested loop configuration, where the intermediate clock tracks the output clock instead of the external source clock, simplifies the design by isolating the non-integral multiple/fraction issue to the first phase-locked circuit, allowing the system to handle multiple external source clocks with different frequencies effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional separate PLL designs are used to handle multiple external source clocks with different frequencies, then the system can support diverse clock sources, but the circuit design complexity increases and costs rise due to non-integral multiple/fraction issues
Solution Approach 1:
The patent merges two separate PLL circuits into a single integrated PLL structure where the first PLL processes the external source clock and the second PLL generates the output clock, with their functions combined in one unified circuit. This integration eliminates the need for separate independent PLL designs, reducing circuit complexity while maintaining the ability to handle multiple external clock frequencies through the frequency conversion mechanism.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the frequency conversion ratio (N/M) in the phase detector to adapt to different external source clock frequencies. By changing the N and M values based on the detected clock frequency, the system can accommodate various external clocks (T-carrier, E-carrier, SDH/SONET, SyncE, GPS, Cesium) without requiring separate hardware designs for each frequency standard.
2Reliability
If separate PLL circuits are used with independent phase detectors and loop filters, then each PLL can independently track its clock source, but the overall system complexity and manufacturing cost increase
Solution Approach 1:
The patent combines the functionality of two separate PLL circuits into one integrated structure where the phase detectors, loop filters, and oscillators work together in a unified manner. The first phase detector processes the external clock, the loop filter conditions the signal, and the second phase detector refines the output, all within a single manufactured unit. This merging maintains independent tracking capability through the cascaded architecture while significantly reducing manufacturing complexity and cost compared to producing two separate independent PLL circuits.
3Measurement precision
If the intermediate clock tracks the external source clock frequency, then frequency synchronization is maintained, but the design becomes complicated when dealing with non-integral multiples of different clock frequencies
Solution Approach 1:
The patent resolves the non-integral multiple issue by dynamically changing the frequency conversion parameters N and M in the phase detector. Instead of requiring the intermediate clock to directly track the external source clock at fixed frequency ratios, the system adjusts N and M based on the detected external clock frequency type (T-carrier, E-carrier, SDH/SONET, etc.). This parameter adaptation maintains precise frequency synchronization while accommodating various clock standards without increasing design complexity.
Solution Approach 2:
The patent introduces an intermediary frequency conversion mechanism between the external source clock and the output clock. The first PLL stage acts as an intermediary that converts the external clock frequency to an intermediate frequency, which is then further processed by the second PLL stage. This intermediary approach allows flexible frequency translation through adjustable N/M ratios, maintaining synchronization accuracy while simplifying the overall design by avoiding direct tracking of diverse external frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a simpler clock holdover circuit design that maintains accurate frequency synchronization without introducing jitter, reducing the complexity and cost associated with handling diverse external clock frequencies.
Implementation Method 1
Each of the PLLs includes its own independent the phase detector (PD)
Implementation Method 2
the loop filter (LP) and the voltage-control oscillator such as the voltage-controlled crystal oscillator (VCXO)
Implementation Method 3
the voltage-control oscillator such as the voltage-controlled crystal oscillator (VCXO) and the numerically controlled oscillator (NCO)
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The embodiments disclose a method and apparatus for implementing the clock holdover in the communication system. The apparatus receives an external source clock and outputs an output clock, and comprises a first phase-locked circuit and a second phase-locked circuit. The first phase-locked circuit is configured for taking the external source clock and a first output clock as input and outputting an intermediate clock, the first output clock is outputted by the second phase-locked circuit and fed back to the first phase-locked circuit. The first phase-locked circuit includes a first digital oscillator, and the first digital oscillator is configured to take the first output clock as a working clock to generate the intermediate clock. The second phase-locked circuit is configured for taking the intermediate clock and a local clock fed by a local oscillator as input, and outputting a second output clock.