Nested SCR ESD Protection Structure for Low Leakage
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Solution Overview
Problem
Existing ESD protection devices suffer from significant current leakage, especially at elevated temperatures, limiting their effectiveness.
Innovation Solution
A semiconductor controlled rectifier (SCR) with a nested N-type well and P-type well layer structure, incorporating a dielectric layer and a parasitic circuit that activates at a threshold voltage, allowing for tunable trigger and holding voltages to manage ESD events with reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection devices are used, then ESD protection function is provided, but current leakage is significant especially at elevated temperatures
Solution Approach 1:
The device employs a dynamic response mechanism where the parasitic SCR circuit remains inactive during normal operation and only activates when ESD stress exceeds the trigger voltage threshold. This dynamic switching between low-leakage standby state and high-current protection state resolves the contradiction by providing effective ESD protection only when needed, minimizing leakage during normal operation.
Solution Approach 2:
The invention changes the electrical parameters of the protection device by using a parasitic SCR structure with可调 trigger voltage and holding voltage. The device transitions from a high-leakage conventional structure to a low-leakage SCR structure where leakage current is minimized until the trigger voltage is reached, at which point the device switches to a low-impedance state for ESD protection.
2Reliability
If trigger voltage is lowered to improve ESD protection responsiveness, then protection effectiveness increases, but device may activate during normal operation
Solution Approach 1:
The parasitic SCR structure provides inherent feedback through its latching mechanism. When the trigger voltage is reached, the SCR turns on and maintains conduction until the current drops below the holding current threshold. This feedback mechanism ensures that once activated by a genuine ESD event, the device remains active long enough to clear the discharge, preventing false deactivation while the parasitic nature prevents false activation during normal operation.
Solution Approach 2:
The device exhibits dynamic voltage characteristics with distinct trigger voltage and holding voltage levels. The trigger voltage determines activation threshold while the holding voltage ensures sustained conduction during ESD events. This dynamic voltage profile allows the device to distinguish between normal voltage fluctuations and genuine ESD stress, preventing false activation while ensuring responsive protection.
3Reliability
If complex ESD protection structures are implemented, then protection performance improves, but device footprint increases
Solution Approach 1:
The invention embeds a parasitic SCR circuit within the existing transistor structure, utilizing the inherent P-N-P-N layers already present in the device. By nesting the ESD protection function within the existing device architecture rather than adding separate protection structures, the solution achieves enhanced protection performance without increasing device footprint.
Solution Approach 2:
The parasitic SCR structure serves multiple functions: it provides ESD protection, voltage clamping, and current limiting all through a single integrated structure. This multi-functionality eliminates the need for separate protection devices, reducing overall footprint while maintaining comprehensive protection performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SCR device provides efficient ESD protection with low leakage current, tunable trigger voltage, and high holding voltage, minimizing substrate noise and latch-up issues while maintaining a compact footprint.
Implementation Method 1
a parasitic circuit is activated within the N-type well layer (110) and the P-type well layer (120) when the anode terminal receives a voltage equal or greater than a first threshold value (Vt1)
Implementation Method 2
a dielectric layer (150) coupled to a gate terminal
Data Source
AI summary
An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes an N-type well layer having a first positive N-type diffusion region coupled to an anode terminal; a P-type well layer having a second positive N-type diffusion region coupled to a cathode terminal; a substrate layer; a N-type buried layer provided between the P-type well layer and the substrate layer; and a dielectric layer coupled to a gate terminal. The N-type buried layer has a third N+ diffusion region coupled to a buried layer terminal. The N-type well layer is provided above the P-type well layer. A parasitic circuit is activated within the N-type well layer and the P-type well layer when the anode terminal receives a voltage equal or greater than a first threshold value.