Nested SR-IOV Virtual Function Mapping Across VM Layers

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Solution Overview

Problem

Nested virtual machines have limited access to single-root input-output virtualization (SR-IOV) capabilities, limiting scalability and functionality in virtual machine nesting scenarios.

Innovation Solution

Mapping memory addresses for device functions associated with an SR-IOV device to enable virtualized SR-IOV capabilities across multiple levels of nested virtual machines, using host and guest memory addresses and input-output memory management units (IOMMUs) to facilitate communication between virtual and physical functions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If nested virtual machines are deployed to increase virtualization density, then hardware utilization and scalability are improved, but access to SR-IOV capabilities is limited

Engineering Contradiction:

ImproveSR-IOV capability accessVSAvoidvirtual machine nesting structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism (host hypervisor with IOMMU) that mediates between the nested virtual machine and the physical SR-IOV device. The host hypervisor translates memory addresses and manages the I/O operations, allowing the nested VM to access SR-IOV capabilities without direct physical access. This resolves the contradiction by enabling SR-IOV access in nested environments while managing the increased complexity through a controlled intermediary layer.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent adds another dimension to the virtualization hierarchy by introducing memory address translation layers. Instead of direct physical access, the system uses multiple memory address spaces (host physical addresses, guest virtual addresses, nested VM virtual addresses) to bridge the gap between nested virtual machines and physical SR-IOV devices. This dimensional translation enables capability access while maintaining the nested structure.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple nested virtual machines access SR-IOV resources, then functionality and scalability are improved, but memory address management complexity increases

Engineering Contradiction:

Improvevirtual machine nesting scalabilityVSAvoidmemory address mapping

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The IOMMU (Input-Output Memory Management Unit) acts as an intermediary that handles memory address translation for I/O operations. It translates between different memory address spaces (host physical, guest virtual, nested VM virtual) and manages the mapping tables that enable multiple nested VMs to access SR-IOV resources. This intermediary mechanism scales productivity while containing address management complexity within a dedicated hardware component.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent uses memory address translation tables that copy and map address spaces between different virtualization layers. Instead of direct physical access, the system creates virtual copies of memory addresses at each layer (host level, guest level, nested level), allowing multiple nested VMs to access the same physical SR-IOV resources through different virtual address spaces without conflict.

Inventive Principle:

Principle #26Copying

3Reliability

If physical function is passed to single nested virtual machine, then SR-IOV access is enabled, but scalability is limited

Engineering Contradiction:

ImproveSR-IOV capability accessVSAvoidnested virtual machine scalability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent segments the SR-IOV device functions into multiple virtual functions that can be independently allocated to different nested virtual machines. Instead of passing the entire physical function to a single nested VM, the system divides the device resources and creates separate virtual function instances that can be distributed across multiple nested VMs, enabling both reliable SR-IOV access and scalability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The host hypervisor with IOMMU creates a universal interface that allows multiple nested virtual machines to access SR-IOV resources through a common memory address translation mechanism. The IOMMU manages a unified set of memory address mappings that can serve any nested VM, making the SR-IOV access mechanism universal rather than dedicated to a single nested machine, thereby enabling scalability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260037296A1Passing single-root input-output virtualization functions to nested virtual machines

Publication Date: 2026.02.05 RED HAT INC

AI summary

Passing communication to or from nested virtual machines can involve one or more mappings. In one example, a host hypervisor can receive, from a physical function of a host computing device, a request generated by a nested virtual function of a nested virtual machine hosted by a guest virtual machine. The request can involve a first guest virtual function of the guest virtual machine, while the nested virtual function can be mapped to a second guest virtual function of the guest virtual machine. The host hypervisor can translate, using a set of mappings stored in a host page table, a guest memory address for the first guest virtual function to a host memory address for the first guest virtual function. The host hypervisor can forward the request to the first guest virtual function using the host memory address determined through translation.