Nested Through-Electrode Substrate Layout for Dense Chip Packaging
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing integration density and reliability while maintaining high performance and speed.
Innovation Solution
The semiconductor device incorporates a base substrate with a core substrate, multiple interconnection substrates, through-electrodes, and insulating layers to enhance integration density and reliability. The through-electrodes penetrate the core substrate and interconnection substrates, with narrower widths and specific central axis alignment, and are electrically connected to the semiconductor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of interconnection layers and through-via structures is increased to improve integration density, then the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent implements nested through-via structures where a second through-via is formed within a first through-via, both penetrating the core substrate. This nesting approach allows multiple interconnection paths to be stacked vertically, increasing integration density without proportionally increasing lateral space requirements or overall device complexity
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by forming through-vias that penetrate the core substrate. Multiple interconnection substrates are stacked vertically with through-vias extending through multiple layers, utilizing the vertical dimension to increase integration density while maintaining manageable complexity through systematic layering
2Quantity of substance
If narrower through-electrodes are used to increase integration density, then the electrical connection reliability may be reduced
Solution Approach 1:
The nested through-via structure allows broader first through-vias to provide robust electrical connections while accommodating narrower second through-vias within them. This nesting enables the system to achieve high integration density with narrow electrodes while the outer broader electrodes maintain reliable electrical connectivity
Solution Approach 2:
The patent employs composite interconnection structures combining conductive electrodes with insulating layers. The first insulating layer is disposed between the first and second through-electrodes, creating a composite structure that provides both electrical connection and electrical isolation, enabling reliable signaling in high-density configurations
3Quantity of substance
If multiple interconnection substrates are added to increase integration density, then the package size and manufacturing complexity increase
Solution Approach 1:
The patent utilizes vertical stacking of multiple interconnection substrates (first and second interconnection substrates) with through-vias penetrating through all layers. This three-dimensional arrangement increases integration density by utilizing the vertical dimension rather than expanding laterally, thereby reducing the overall package footprint while accommodating multiple interconnection layers
Data Source
AI summary
A semiconductor device includes a base substrate and a semiconductor chip disposed on the base substrate. The base substrate includes a core substrate, first interconnection substrates disposed on a first surface of the core substrate and a second surface opposite to the first surface, a first through-electrode penetrating the core substrate, a second through-electrode penetrating the core substrate and the first interconnection substrates, having a same central axis as the first through-electrode, and having a width narrower than a width of the first through-electrode, and a first insulating layer disposed between the first through-electrode and the second through-electrode and surrounding at least a portion of a side surface of the second through-electrode.