Nested Trench Capacitor Structure for Higher Capacitance Density
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Solution Overview
Problem
Conventional Metal-Insulator-Metal (MIM) capacitors face challenges in increasing capacitance density due to difficulties in etching trenches with larger aspect ratios, leading to potential electrode connection issues from oblique angles, which hinder the increase in capacitor numbers required for 5G antenna tuners.
Innovation Solution
A parallel-connected capacitor structure is fabricated using a substrate with trenches having perpendicular sidewalls, where multiple electrode layers are formed through electroplating processes, with a capacitor dielectric layer between each pair of electrodes and conductive plugs contacting specific layers, allowing for easier dry etching and higher capacitance density without electrode connection issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the aspect ratio of the trench is increased to increase capacitance density, then the capacitance density increases, but the etching difficulty increases and oblique angles occur at the trench edge
Solution Approach 1:
The patent transitions from a single capacitor per trench to multiple capacitors stacked in vertical layers within the same trench. By utilizing the vertical dimension to create multiple electrode layers (first electrode layer, second electrode layer, third electrode layer, etc.) separated by dielectric layers, the design achieves higher capacitance density without increasing trench depth, thus maintaining a small aspect ratio and avoiding etching difficulties.
Solution Approach 2:
The patent implements a nested structure where multiple capacitor elements are contained within a single trench. Each capacitor consists of electrodes and dielectric layers that are stacked concentrically, with the first capacitor containing a first electrode and dielectric layer, the second capacitor containing a second electrode and dielectric layer, and so on. This nesting approach maximizes the use of available space while maintaining manufacturing feasibility.
2Quantity of substance
If the aspect ratio of the trench is increased to increase the number of capacitors per unit area, then the number of capacitors increases, but electrode connection issues occur due to oblique angles
Solution Approach 1:
The patent uses vertical stacking of multiple electrode layers to increase the number of capacitors per unit area without increasing trench depth. This approach maintains perpendicular sidewalls that prevent oblique angle formation, ensuring reliable electrode connections and avoiding the connection issues that would arise from high aspect ratio trenches.
Solution Approach 2:
The patent divides a single capacitor structure into multiple discrete capacitor elements stacked in sequence. Each capacitor element consists of separate electrode layers and dielectric layers that are independently formed, allowing for reliable connections between adjacent electrodes while maintaining a compact vertical arrangement that does not require deep trenches.
3Quantity of substance
If multiple electrode layers are formed in a trench with small aspect ratio, then the number of capacitors per unit area increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs a periodic manufacturing process where alternating layers of electrodes and dielectric materials are deposited in a repeating sequence. The process involves forming a first electrode layer, then a first dielectric layer, then a second electrode layer, then a second dielectric layer, and so on. This periodic deposition pattern simplifies the manufacturing process by using the same steps repeatedly rather than requiring different complex processes for each layer.
Solution Approach 2:
The patent uses universal deposition and etching processes that can form multiple types of layers (electrodes and dielectric layers) using the same equipment and methodology. The electroplating process, for example, can be used to form multiple electrode layers with different materials by simply changing the plating solution, and the dielectric layers can be formed using standard deposition techniques, making the overall process highly versatile and manageable despite the multiple layers involved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of capacitors with a small aspect ratio, facilitating easier dry etching and increasing the number of capacitors per unit area while maintaining high capacitance density, addressing the limitations of conventional technologies.
Implementation Method 1
a plurality of electroplating processes is performed to form a plurality of electrode layers filling in the trenches
Data Source
AI summary
A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.