Nested Vertical Capacitors for Display Device Area Reduction
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Solution Overview
Problem
Current display devices face challenges in minimizing the area of auxiliary capacitors and reducing dead space, which are essential for high-speed driving and compact design in display technologies like OLEDs.
Innovation Solution
The display device incorporates two capacitors disposed up and down to minimize the auxiliary capacitor area and includes two boost capacitors in scan and emission drivers, which are also positioned up and down to reduce dead space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If auxiliary capacitors are minimized in area, then device compactness is improved, but high-speed driving capability may be compromised
Solution Approach 1:
The patent implements a nested capacitor structure where a first capacitor and a second capacitor are vertically stacked and share common conductive patterns. The first capacitor includes a first conductive pattern, first insulating layer, and second conductive pattern, while the second capacitor uses the second conductive pattern as one of its electrodes and adds a third conductive pattern. This nesting allows two capacitors to occupy the same horizontal footprint, minimizing auxiliary capacitor area while providing sufficient total capacitance for high-speed driving operations.
Solution Approach 2:
The patent transitions from a planar capacitor arrangement to a three-dimensional vertical stacking configuration. By disposing capacitors in the vertical dimension rather than spreading them horizontally, the design achieves both compactness (reduced horizontal area) and adequate capacitance (multiple stacked capacitors), resolving the contradiction between area minimization and performance maintenance.
2Area of stationary object
If dead space is reduced through compact capacitor positioning, then device efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple capacitor structures into a unified vertical stack where conductive patterns and insulating layers are shared between capacitors. The second conductive pattern serves as both the top electrode of the first capacitor and the bottom electrode of the second capacitor. This merging reduces the number of discrete components and simplifies the manufacturing process while eliminating dead space that would exist between separate capacitor structures.
Solution Approach 2:
The conductive patterns and insulating layers in the stacked capacitor structure serve multiple functions simultaneously. The second conductive pattern functions as both an electrode for the first capacitor and an electrode for the second capacitor. The intermediate insulating layer serves as both the dielectric for the first capacitor and the structural separator for the second capacitor. This multi-functionality reduces component count and manufacturing steps while maximizing space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a more compact design that supports high-speed driving and reduces dead space, enhancing the performance and efficiency of the display device.
Implementation Method 1
a first conductive pattern disposed on the first gate electrode such that the first conductive pattern and the first gate electrode constitute a first capacitor, a second conductive pattern disposed on the first capacitor, a third conductive pattern disposed on the second conductive pattern such that the third conductive pattern and the second conductive pattern constitute a second capacitor
Data Source
AI summary
A display device may include a substrate, a first transistor disposed on the substrate and including a first gate electrode, a first conductive pattern disposed on the first gate electrode such that the first conductive pattern and the first gate electrode constitute a first capacitor, a second conductive pattern disposed on the first capacitor, a third conductive pattern disposed on the second conductive pattern such that the third conductive pattern and the second conductive pattern constitute a second capacitor, and a light emitting structure disposed on the second capacitor.