Nested Via Hole Structure for Fluorine Gas Venting in Array Substrates

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Solution Overview

Problem

The existing display panel manufacturing process results in fluorine-containing compounds remaining in via holes, leading to bubble formation on the pixel electrode layer, which causes abnormal contact with the source/drain and affects the quality of the product.

Innovation Solution

Incorporating a second via hole within the first via hole to allow the escape of fluorine-containing gases, thereby preventing bubble formation and improving contact between the pixel electrode layer and the source/drain.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If dry etching with fluorine-containing gas is used to form via holes, then via holes can be effectively formed for electrical connection, but fluorine-containing compounds remain in the via holes causing bubble formation on the pixel electrode layer

Engineering Contradiction:
Improvevia hole formation qualityVSAvoidbubble formation on pixel electrode layer
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The via hole structure is segmented into two parts: a first via hole for electrical connection and a second via hole for gas escape. This segmentation allows the first via hole to maintain electrical functionality while the second via hole provides a dedicated pathway for fluorine-containing compound removal, preventing bubble formation on the pixel electrode layer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second via hole acts as an intermediary structure that mediates between the fluorine-containing compounds trapped in the first via hole and the external environment. It provides a controlled escape route for these harmful compounds without interfering with the electrical connection function of the first via hole

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If fluorine-containing compounds remain in via holes, then via hole structure is simple, but bubbles form on pixel electrode layer causing abnormal contact

Engineering Contradiction:
Improvevia hole structure complexityVSAvoidcontact quality between pixel electrode layer and source/drain
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The via hole system is divided into functionally distinct first and second via holes. The first via hole maintains electrical connection with minimal structural complexity, while the second via hole is specifically designed for gas venting, thereby preserving contact reliability without significantly increasing overall structural complexity

Inventive Principle:
Principle #1Segmentation

3Object-generated harmful factors

If second via hole is added in first via hole, then bubble formation is prevented, but via hole structure becomes more complex

Engineering Contradiction:
Improvebubble formation preventionVSAvoidvia hole structure complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The second via hole is nested within the first via hole structure, with the opening of the second via hole positioned within the opening of the first via hole. This nesting arrangement allows the gas escape function to be integrated into the existing via hole footprint, minimizing the increase in structural complexity while effectively preventing bubble formation

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11454852B2Array substrate, manufacturing method thereof, and display panel
Publication Date: 2022.09.27 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US11454852B2 patent drawing
  • US11454852B2 patent drawing
  • US11454852B2 patent drawing

AI summary

The present application provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a substrate, a driving circuit layer located on the substrate, and a pixel electrode layer located on the driving circuit layer, wherein the pixel electrode layer is electrically connected to the driving circuit layer through a first via hole; and wherein the pixel electrode layer further includes at least one second via hole located in the first via hole, and the second via hole exposes a part of the driving circuit layer.