Nested Via Interconnection Structure for Semiconductor Devices
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Solution Overview
Problem
The increased demand for high-performance, high-speed semiconductor devices with multi-functionality has led to reduced transistor sizes, resulting in decreased interconnection sizes, which face challenges due to increased resistance and capacitance, making high-speed operations difficult.
Innovation Solution
A semiconductor device with a specific interconnection structure that includes inclined vias and interconnection layers, where the second via covers the upper surface and side surfaces of the first interconnection layer, and the second interconnection layer is wider in one direction than the first, reducing parasitic capacitance and resistance through a dual damascene process and low-k dielectric materials with high carbon content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of interconnections is decreased to achieve high-density integration, then the degree of integration is improved, but resistance and capacitance of interconnections increase
Solution Approach 1:
The patent implements a nested via structure where a second via is formed inside the protruding portion of a first via, creating multiple conductive paths through the same vertical space. This nesting approach increases the effective conduction area without increasing the horizontal footprint, thereby reducing resistance and improving electrical characteristics while maintaining high-density integration.
Solution Approach 2:
The patent transitions from two-dimensional interconnection scaling to three-dimensional structuring by creating vias with protruding portions that extend vertically. The second via is positioned within this protruding portion, utilizing the vertical dimension to increase conduction area. This dimensional transition allows for reduced resistance and capacitance without sacrificing integration density.
2Speed
If the size of transistors is decreased to achieve high-speed operations, then the operating frequency is improved, but interconnection resistance and capacitance increase
Solution Approach 1:
The nested via structure with multiple conductive paths increases the effective conduction area, reducing resistance in the interconnection. This allows for decreased transistor size and higher operating frequencies while maintaining good electrical characteristics through the reduced-resistance nested via pathways.
Solution Approach 2:
The patent employs low-k dielectric materials with high carbon content (such as SiOC or SiOCH) as fillers in the via structures. These composite material choices minimize parasitic capacitance between interconnections, enabling high-speed operations with reduced RC time delay even as transistor dimensions are scaled down.
3Reliability
If low-k dielectric materials with high carbon content are used to minimize capacitance, then parasitic capacitance is reduced, but structural stability may be compromised
Solution Approach 1:
The patent uses low-k dielectric materials with high carbon content (SiOC or SiOCH) as fillers in the nested via structures. These materials provide low parasitic capacitance while the nested via design with multiple conductive paths and the protruding portion structure distribute mechanical stresses, maintaining structural stability despite the use of softer, lower-k materials.
Solution Approach 2:
The nested via structure with second via inside the protruding portion of the first via creates a mechanically robust configuration. This nested design distributes mechanical loads and provides structural support that compensates for the potentially lower mechanical strength of high-carbon-content low-k dielectric materials, maintaining overall structural stability while achieving low capacitance.
Data Source
AI summary
A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.