Nested VM Memory Access via Shadow Page Tables
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Solution Overview
Problem
Nested virtualization systems face performance hindrances and security risks due to the need for Level 2 VMs to pause processing and use additional CPU resources when updating page table entries in the IOMMU, especially when a PCI device modifies its accessibility to guest memory pages.
Innovation Solution
Implementing a shadow page table configuration that allows Level 2 VMs direct access to the second-level page table of the IOMMU, enabling them to update page table entries without triggering interrupts, thus reducing resource usage and enhancing security by protecting memory pages from malicious or faulty PCI devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Level 2 VMs use the traditional page table update mechanism in IOMMU, then memory access security is maintained, but processing performance deteriorates due to interrupts and additional CPU resources being consumed
Solution Approach 1:
The patent segments the page table structure into two separate tables: a first page table managed by the Level 1 hypervisor and a second page table managed by the Level 2 VM. This segmentation allows the Level 2 VM to independently update its own page table entries without triggering interrupts to the Level 1 hypervisor, thereby maintaining security while improving performance. The IOMMU is configured to use both tables in a nested manner, with the second table being accessible only to the Level 2 VM.
Solution Approach 2:
The patent introduces a shadow page table as an intermediary structure between the Level 1 hypervisor's page table and the Level 2 VM's page table. The shadow page table allows the Level 2 VM to perform page table updates locally without directly affecting the Level 1 hypervisor's memory management, thus eliminating the need for interrupts while maintaining security boundaries.
2Measurement precision
If Level 2 VMs pause processing to update page table entries, then memory management accuracy is ensured, but resource usage increases due to additional CPU resources and interrupts
Solution Approach 1:
By segmenting the page table into separate first and second tables with distinct management responsibilities, the patent enables the Level 2 VM to perform accurate memory management updates independently without pausing processing or consuming additional CPU resources from the host system.
Solution Approach 2:
The Level 2 VM is granted the capability to self-manage its own page table entries through direct access to the second page table in the IOMMU. This self-service mechanism eliminates the need for the Level 2 VM to pause and request assistance from the Level 1 hypervisor, thereby reducing CPU resource usage while maintaining memory management accuracy.
3Stability of the object's composition
If traditional page table mechanisms are used in nested virtualization, then system stability is maintained, but performance is hindered due to interrupt-driven updates
Solution Approach 1:
The patent segments the page table management responsibilities between the Level 1 hypervisor and Level 2 VM, allowing non-blocking updates in the Level 2 VM. The IOMMU is configured to respect these segmentation boundaries while maintaining overall system stability through proper isolation and permission controls.
Solution Approach 2:
The patent implements preliminary configuration of the IOMMU to recognize and accommodate the nested page table structure before memory access operations occur. This preliminary setup enables efficient, interrupt-free page table updates by pre-establishing the necessary translation paths and permission rules.
Data Source
AI summary
Systems and methods for memory management for nested virtual machines. An example method may comprise running, by a host computer system, a Level 0 hypervisor managing a Level 1 virtual machine running a Level 1 hypervisor, wherein the Level 1 hypervisor manages a Level 2 virtual machine, wherein the Level 2 virtual machine is associated with a Peripheral Component Interconnect (PCI) device; generating, by the Level 0 hypervisor, a Level 1 page table by combining records from the guest page table with records from a host page table maintained by the Level 0 hypervisor; generating a Level 2 page table comprising a plurality of Level 2 page table entries; and causing a device driver of the Level 2 virtual machine to use the Level 2 page table for second level address translation.