Nested Well ESD Protection for High-Voltage Integrated Circuits
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Solution Overview
Problem
Existing devices for protecting integrated circuits against electrostatic discharges are inadequate for high power supply voltages and have a significant bulk, limiting their effectiveness and practicality.
Innovation Solution
The design includes a doped semiconductor substrate with specific well structures and resistive elements, allowing for efficient electrostatic discharge protection across a wide range of voltages, including those greater than 10 V, by utilizing a doped semiconductor substrate with multiple well layers and resistive elements to manage potential differences and prevent irreversible damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional protection devices are used, then electrostatic discharge protection is provided, but the device bulk is significant and incompatible with high power supply voltages
Solution Approach 1:
The patent implements nested doped wells where a first doped well is formed within a second doped well, which is itself formed within a third doped well. This nested configuration allows multiple protection functions to be integrated in a compact vertical arrangement, reducing the horizontal footprint and overall device bulk while maintaining comprehensive electrostatic discharge protection capability
Solution Approach 2:
The patent transitions from planar protection structures to a vertical three-dimensional configuration by forming multiple doped wells at different depths within the semiconductor substrate. This vertical stacking approach enables high voltage protection functionality without increasing the lateral device area, effectively addressing the bulk reduction requirement
2Reliability
If conventional protection devices are used, then electrostatic discharge protection is provided, but compatibility with high power supply voltages greater than several tens of volts is not achieved
Solution Approach 1:
The patent applies different doping types and concentrations to specific regions: a first doped well with first conductivity type, a second doped well with second conductivity type nested within it, and a third doped well with first conductivity type containing the second. This localized differentiation of electrical properties creates distinct functional zones that enable the device to handle high power supply voltages while maintaining effective electrostatic discharge protection
Solution Approach 2:
The patent creates a composite doped structure combining multiple semiconductor regions with different conductivity types and doping levels. The alternating pattern of first and second conductivity types in nested wells forms a composite structure that provides both high voltage blocking capability and electrostatic discharge protection, achieving compatibility with power supply voltages greater than several tens of volts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects integrated circuits from electrostatic discharges while maintaining a compact form factor, enabling compatibility with higher power supply voltages without increasing bulk or complicating manufacturing processes.
Implementation Method 1
a doped semiconductor substrate with specific well structures and resistive elements, allowing for efficient electrostatic discharge protection across a wide range of voltages
Implementation Method 2
resistive elements to manage potential differences and prevent irreversible damage
Data Source
AI summary
An electronic device includes a doped semiconductor substrate of a first conductivity type. A first doped well of a second conductivity type opposite to the first conductivity type extends into the doped semiconductor substrate from a surface thereof. A second doped well of the first conductivity type is located in the first well. A third electrically-insulating well is located in the second well. A fourth doped well of the first conductivity type is located in the third well. First, second, and third doped regions of the first conductivity type are respectively located in the doped semiconductor substrate, the second doped well and the fourth doped well. The first, second, and third doped regions have doping levels greater than a doping level of the doped semiconductor substrate. A fourth doped region the second conductivity type is located in the fourth doped well adjacent the second doped region.