Nested Wire Tamper Detection in Chip Packages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current chip packaging lacks effective tamper resistance, making it vulnerable to surreptitious access and reverse engineering.
Innovation Solution
A chip package structure featuring a lead frame with inner and outer lead fingers, where wires from the inner lead fingers connect to bond pads on the chip, and a tamper detection circuit is integrated to monitor signals for any tampering attempts, using a pseudo signal to enhance security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional chip packaging is used, then manufacturing simplicity is maintained, but tamper resistance is insufficient
Solution Approach 1:
The patent implements nested wire structures where outer wires extend from outer lead fingers to locations interior to bond pads, and inner wires extend from inner lead fingers to bond pads. The outer wires are positioned exterior to the inner wires, creating a nested configuration that provides tamper detection capability while maintaining integration within the chip package structure.
Solution Approach 2:
The patent introduces a tamper detection circuit that couples to the outer wires, serving as an intermediary mechanism to detect tampering attempts. This circuit monitors the outer wires for tamper signals without directly interfering with the inner wires' connection function, thus adding security while preserving the original electrical connections.
2Reliability
If wire routing is simplified, then manufacturing ease is improved, but security monitoring capability is reduced
Solution Approach 1:
The patent segments the wire connections into distinct outer wires and inner wires with different functions. Outer wires are dedicated to tamper detection, extending from outer lead fingers to locations interior to bond pads, while inner wires handle signal transmission to bond pads. This segmentation allows each wire type to be optimized for its specific function, with the tamper detection circuit coupling to outer wires to monitor for tampering attempts.
Data Source
AI summary
Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach paddle, a plurality of outer lead fingers, and a plurality of inner lead fingers located between the outer lead fingers and the die attach paddle. A chip is attached to the die attach paddle. The chip includes a surface having an outer boundary and a plurality of bond pads arranged proximate to the outer boundary. A first plurality of wires extend from the outer lead fingers to respective locations on the surface of the chip that are interior of the outer boundary relative to the bond pads. A tamper detection circuit is coupled with the first plurality of wires. A second plurality of wires extend from the inner lead fingers to the bond pads on the chip. The second plurality of wires are located between the lead frame and the first plurality of wires.