Net Pattern Scaling for Accurate Wire Delay Estimation
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Solution Overview
Problem
The increasing wire delays relative to gate delays in circuit designs due to technology scaling make it difficult to achieve design closure during physical synthesis, as existing wire delay estimates are often inaccurate, leading to prolonged iterations of optimization.
Innovation Solution
The method involves analyzing preliminary routing information to identify timing-critical nets, assigning them to routing layers, and updating scaling factors for net patterns based on their physical attributes, which improves the accuracy of estimated net delays and correlations between placement-based and routing-based delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If average RC values are used for calculating wire delay estimates, then the calculation process is simple and fast, but the accuracy of delay estimates deteriorates
Solution Approach 1:
The patent applies local quality by creating net-specific RC models instead of using uniform average values. Each net pattern (short, medium, long) receives customized RC parameters derived from its specific physical characteristics and routing behavior, thereby improving delay estimation accuracy for each local net category while maintaining overall system manageability
Solution Approach 2:
The patent segments the circuit design into different net patterns based on physical attributes such as net length, routing layer, and congestion level. By dividing nets into categories (short, medium, long) and developing specific RC models for each segment, the system achieves higher overall accuracy without requiring a single overly complex universal model
2Reliability
If multiple iterations of placement and routing optimization are performed, then design closure is achieved, but the time required increases significantly
Solution Approach 1:
The patent performs preliminary routing analysis before final placement and routing optimization. By analyzing preliminary routing information to identify timing-critical nets and establish net patterns early in the design process, the system prepares accurate delay models in advance, enabling faster convergence during subsequent optimization iterations and reducing the total time to achieve design closure
3Ease of operation
If wire delay estimates are improved through detailed analysis, then placement and routing decisions are more accurate, but the complexity of the EDA tool increases
Solution Approach 1:
The patent changes parameters by dynamically adjusting RC values based on net-specific characteristics such as length, routing layer, and congestion. Instead of using fixed average parameters, the system modifies RC parameters according to the actual physical conditions of each net pattern, enabling more accurate delay predictions without requiring fundamentally new tool architecture
Data Source
AI summary
A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations.