Net Pruning via Marker Layer Segmentation for Circuit Validation
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Solution Overview
Problem
The increasing complexity of integrated circuit designs leads to inefficiencies in testing and validation due to prolonged time in performing electrical connectivity analysis, particularly when checking for violations across multiple metal and polysilicon layers, necessitating a faster and more efficient process for rule violations.
Innovation Solution
A method and system for pruning nets in circuit designs that involves receiving data on net layers, accessing a connect database, determining the existence of a marker layer, and pruning nets not connected to it, thereby improving the efficiency and speed of electrical rule violations checks by maintaining only connected and marker-interacting nets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If electrical connectivity analysis is performed across all metal and polysilicon layers to check for design rule violations, then validation completeness is improved, but analysis time increases significantly
Solution Approach 1:
The patent extracts and removes unnecessary net layers from the connectivity analysis. By identifying and excluding net layers that do not connect to marker layers or other required layers, the system performs validation only on relevant portions of the circuit, significantly reducing analysis time while maintaining completeness for critical connections.
Solution Approach 2:
The patent segments the net layers into two categories: those that connect to marker layers (and should be included in analysis) and those that do not (and can be excluded). This segmentation allows the validation system to process only the essential connections, reducing overall analysis time while maintaining validation reliability for critical paths.
2Measurement precision
If all net layers are included in electrical connectivity analysis, then detection accuracy for design rule violations is improved, but processing speed decreases
Solution Approach 1:
The system extracts and removes net layers that do not connect to marker layers from the connectivity analysis. This extraction maintains detection accuracy for critical design rule violations while significantly improving processing speed by analyzing only the essential net layers that could contain violations.
Solution Approach 2:
The system performs preliminary identification of marker layers and their connections before the main connectivity analysis. This preliminary action filters out unnecessary net layers in advance, allowing the main analysis to proceed at higher speed while maintaining accuracy for the remaining critical connections.
Data Source
AI summary
A method of pruning nets in a circuit design includes, in part, receiving data representative of net layers associated with the circuit design, and accessing a connect database associated with the circuit design. The connect database includes data representative of electrical connections associated with the circuit design. The method further includes, in part, determining whether a marker layer exists in the net layers, and pruning nets that are not connected to the marker layer if the marker layer is determined to exist. The marker layer, which is not stored in the connect database, designates a connection between at least a pair of nets in the circuit design.