Net Routing Constraints for Accurate Wire Delay Estimation
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Solution Overview
Problem
The increasing wire delays relative to gate delays in circuit designs due to technology scaling make it difficult to achieve design closure during physical synthesis, as current EDA tools rely on inaccurate wire delay estimates, leading to prolonged iteration times in optimizing placement and routing.
Innovation Solution
Analyzing net information to derive attribute ranges for binning nets into Gaussian distributions, generating net routing constraints and scaling factors that improve the correlation between estimated and actual routing delays, and applying these constraints during placement-based optimizations to enhance the accuracy of delay estimates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If average resistance and capacitance values are used for calculating wire delay estimates, then the calculation process is simple and fast, but the accuracy of wire delay estimates deteriorates
Solution Approach 1:
The patent changes the parameters used in delay estimation from fixed average values to dynamic values based on net patterns. By deriving net routing constraints from post-route information and using these to classify nets into patterns, the estimation uses tailored resistance and capacitance values for each pattern, significantly improving accuracy while managing complexity through systematic classification
Solution Approach 2:
The patent segments the circuit design's nets into different patterns based on their physical attributes and routing characteristics. By dividing nets into distinct categories (patterns) with similar behaviors, the system can apply specific delay estimation parameters to each segment, improving overall accuracy without requiring completely complex individual analysis of each net
2Reliability
If multiple iterations of placement and routing optimization are performed to achieve design closure, then timing requirements are met, but the time required to reach closure increases
Solution Approach 1:
The patent performs preliminary action by deriving net routing constraints from post-route information before the actual placement and routing optimization begins. By pre-classifying nets into patterns and establishing routing constraints upfront, the system guides the placement and routing process to produce better initial results, reducing the number of iterations needed to achieve timing closure
Solution Approach 2:
The patent implements feedback by using post-route information (actual routing results) to derive net routing constraints that are then applied in subsequent placement and routing iterations. This closed-loop approach continuously improves the accuracy of delay estimation and routing decisions, accelerating convergence to design closure
3Measurement precision
If pattern-based net routing constraints are derived and applied, then the correlation between placement-based and routing-based delays improves, but the initial analysis and constraint generation process becomes more complex
Solution Approach 1:
The patent performs the complex analysis and constraint generation as a preliminary action that is done once before the main placement and routing optimization process. By deriving net routing constraints upfront from available post-route information, the system establishes accurate patterns that guide subsequent iterations, improving delay correlation without repeating the complex analysis in every iteration
Data Source
AI summary
A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design.