Netlist Interconnect Adjustment for Local Clock Controller Timing
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Solution Overview
Problem
Current placement techniques for integrated circuits (ICs) do not adequately address timing issues that arise post-silicon, particularly for components like launch and capture latches that share a common local clock buffer controller.
Innovation Solution
A computer-implemented method that determines a netlist for an IC design, identifies timing paths with shared local clock buffer controllers, calculates slack values, and adjusts interconnects to minimize the number of launch and capture latches sharing the same local clock buffer controller, thereby improving timing accuracy post-silicon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current placement techniques are used for cell placement in IC design, then the placement is adequate for data interconnections, but timing issues arise post-silicon for latches sharing common local clock buffer controllers
Solution Approach 1:
The patent applies preliminary action by analyzing the netlist during the design phase to identify timing paths where launch and capture latches share common local clock buffer controllers. The system calculates slack values and scores these timing paths, then adjusts interconnects before silicon fabrication to prevent post-silicon timing issues. This proactive approach resolves timing problems before they manifest in the physical device, eliminating the need for post-silicon adjustments.
2Reliability
If delaying techniques are used post-silicon to address timing issues, then certain timing problems can be corrected, but latches sharing common local clock buffer controllers cannot benefit from adjustment
Solution Approach 1:
The system performs timing analysis and interconnect adjustment during the design phase, before silicon fabrication. By identifying timing paths with shared clock buffer controllers and calculating their slack values, the system proactively modifies the netlist to eliminate problematic configurations. This prevents the timing issues that would otherwise require post-silicon delaying techniques, ensuring all latches can benefit from proper timing adjustment capability.
Solution Approach 2:
The patent creates an optimized copy of the netlist with adjusted interconnects that eliminates timing path problems. This virtual model allows the design team to evaluate different interconnect configurations and select the optimal solution before fabrication, ensuring the physical implementation has built-in timing correctness without requiring post-silicon modifications.
3Adaptability or versatility
If the number of timing paths with shared local clock buffer controllers is reduced, then post-silicon clock delay tuning becomes possible, but additional design and analysis steps are required
Solution Approach 1:
The system creates and analyzes a virtual copy of the netlist to evaluate timing paths and identify configurations where launch and capture latches share clock buffer controllers. This virtual modeling approach allows comprehensive timing analysis without affecting the physical device complexity. The optimized netlist configuration is then implemented, enabling post-silicon clock delay tuning while the analysis complexity is contained in the design phase software processes.
Data Source
AI summary
Aspects of the invention include determining a netlist for an integrated circuit design, wherein the netlist includes a design for placement of a plurality of latches, determining a set of timing paths, wherein each timing path includes a capture latch and at least one launch latch connected to a same local clock buffer controller through a local clock buffer OR circuit, calculating a slack value for each timing path, determining one or more candidate timing paths from the set of timing paths, wherein the one or more candidate timing paths have a slack value below a threshold slack value, calculating a score for each candidate timing path based on a count of a number of launch-capture latch pairs, adjusting an interconnect for a first candidate timing path based on the first candidate timing path having a highest score, and generating an updated netlist based on the adjusting the interconnect.