Netlist Partitioning for Data Processing Engine Arrays

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Solution Overview

Problem

There is a lack of efficient processor-based systems capable of compiling applications for heterogeneous data processing architectures, particularly for data processing engine (DPE) arrays, which require complex mapping and communication networks, leading to high runtime issues and convergence problems in previous techniques.

Innovation Solution

The implementation of a method that partitions a netlist into smaller sub-graphs using integer linear programming (ILP) algorithms for global and detailed mapping, allowing for efficient placement of program nodes and buffers within a DPE array, reducing runtime and achieving structured placement results.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional compilation methods are used for DPE arrays, then mapping can be performed, but runtime is excessively high and convergence problems occur

Engineering Contradiction:
Improvecompilation speedVSAvoidruntime
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent divides the netlist into multiple partitions or clusters, transforming the single large-scale mapping problem into several smaller sub-problems. This segmentation enables parallel processing and reduces the computational complexity, thereby decreasing runtime while maintaining mapping quality.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If complex mapping algorithms are used for DPE arrays, then placement accuracy can be achieved, but convergence problems and high runtime occur

Engineering Contradiction:
Improveplacement accuracyVSAvoidconvergence
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent performs preliminary clustering of the netlist before the actual mapping process. This pre-processing step organizes the data into manageable groups with defined connectivity, which facilitates subsequent mapping operations and ensures reliable convergence by reducing the search space and eliminating random initialization issues.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If the entire netlist is processed at once, then complete mapping can be achieved, but runtime becomes unacceptably high

Engineering Contradiction:
Improvemapping completenessVSAvoidcompilation efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The netlist is divided into multiple partitions that can be processed independently and in parallel. Each partition is mapped separately using the same algorithm, ensuring complete coverage while significantly improving compilation efficiency through parallel execution and reduced per-partition complexity.

Inventive Principle:
Principle #1Segmentation

4Manufacturing precision

If detailed mapping is performed without global mapping, then detailed placement can be achieved, but overall optimization and convergence are problematic

Engineering Contradiction:
Improvedetailed placement precisionVSAvoidoverall convergence
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent implements a two-stage approach where global mapping is performed first to establish the overall structure and connectivity of partitions. This preliminary global view provides a foundation for subsequent detailed mapping, ensuring both local precision and global optimization, thereby achieving reliable convergence.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10783295B1Netlist partitioning for designs targeting a data processing engine array
Publication Date: 2020.09.22 XILINX INC
  • US10783295B1 patent drawing
  • US10783295B1 patent drawing
  • US10783295B1 patent drawing

AI summary

An example method for compiling includes, by a processor-based system: obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; partitioning the netlist into a plurality of partitions; for each of the plurality of partitions: generating a global mapping of the program nodes based on a representation of the array of data processing engines and using an integer linear programming (ILP) algorithm; generating a detailed mapping of the program nodes based on the global mapping; and translating the detailed mapping for each of the plurality of partitions to a file.