Netlist Comparison via Pin Connection Arrays
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Solution Overview
Problem
Existing EDA software struggles to accurately compare netlists between schematic diagrams and PCBs due to differences in network names, leading to potential disconnections or new connections being added without detection, especially when converting between different software products.
Innovation Solution
A method for netlist comparison that involves acquiring and processing schematic diagram and PCB netlist files to form arrays representing pin connection relationships, comparing these arrays to identify differences, and outputting results to ensure accurate correspondence and connection integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If netlist comparison is performed based on network names in existing EDA software, then the comparison process is simple, but the comparison accuracy deteriorates when network names change during software conversion
Solution Approach 1:
The patent extracts the network name from the comparison process and focuses only on the pin connection relationships. By removing the network name element that causes inaccuracies during software conversion, the comparison is performed solely on the essential connection topology (pin-to-pin relationships), thereby maintaining comparison simplicity while improving accuracy.
Solution Approach 2:
The patent segments the netlist comparison into two independent parts: network name comparison and pin connection relationship comparison. By separating these elements, the method allows pin connection relationships to be compared accurately even when network names differ, resolving the contradiction between simple operation and accurate measurement.
2Productivity
If netlist comparison relies on network name matching, then the comparison speed is fast, but the reliability of connection verification deteriorates due to undetected disconnections or new connections
Solution Approach 1:
The patent extracts and removes the network name from the core verification process, comparing only pin connection relationships. This extraction maintains fast comparison speed while significantly improving reliability by detecting actual connection changes (disconnections or new connections) that would be missed when relying solely on network name matching.
Solution Approach 2:
The patent implements a feedback mechanism where pin connection relationships are verified and compared, providing accurate feedback on whether connections are maintained, disconnected, or newly added. This feedback loop ensures reliable connection verification while maintaining efficient comparison throughput.
3Adaptability or versatility
If EDA software converts netlists between different formats, then the adaptability between software products improves, but the consistency of network names deteriorates causing comparison failures
Solution Approach 1:
The patent extracts the network name element that becomes inconsistent during software conversion and excludes it from the comparison process. By comparing only pin connection relationships, the method maintains adaptability across different EDA software formats while avoiding the network name consistency problem that arises during conversion.
Solution Approach 2:
The patent changes the comparison parameter from network names (which vary during software conversion) to pin connection relationships (which remain stable). This parameter change allows the system to adapt to different software formats while maintaining consistent and accurate comparison results.
Data Source
AI summary
Disclosed is a method for performing netlist comparison based on a pin connection relationship of a component, comprising the steps: acquiring a schematic diagram netlist file generated by a schematic diagram, and acquiring a PCB netlist file generated by a PCB; reading a network in the schematic diagram netlist file, forming a netlist connection relationship corresponding to each network into a schematic diagram array, all schematic diagram arrays forming a schematic diagram array set; reading a network in the PCB netlist file, forming a netlist connection relationship corresponding to each network into a PCB array, all PCB arrays forming a PCB array set; and comparing the schematic diagram array set with the PCB array set, and outputting differences between the two array sets. The present disclosure merely compares the connection relationship of components. With regard to the condition where a pin connection relationship of an element does not change but a network name changes, occurring during the conversion of different pieces of EDA software, and the present disclosure can effectively guarantee the accuracy of a connection after a schematic diagram and a PCB network are converted. The present disclosure can be widely applied to netlist comparison systems of pin connection relationships of various EDA software components.