Netlist Reduction for Memory Abstraction in Hardware Verification
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Solution Overview
Problem
Current model checking technologies face difficulties in efficiently verifying complex hardware designs with wide datapaths and large memories, as they require time-consuming designer annotations and computationally hard abstractions, and are limited in analyzing sequential systems and unbounded properties.
Innovation Solution
A netlist reduction method that abstracts circuit designs with memories into smaller representations, using a directed acyclic graph data structure to reduce memory slots and bit widths, allowing for standard verification tools to check specified properties with reduced computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional model checking is applied to hardware designs with large memories, then verification completeness is improved, but computational complexity increases making the problem intractable
Solution Approach 1:
The patent extracts and separates memory components from the rest of the circuit design, creating an abstracted representation that focuses only on relevant memory slots. This extraction allows verification to proceed on a reduced model rather than the complete design, resolving the contradiction between verification completeness and computational complexity.
Solution Approach 2:
The patent segments the large memory into smaller, manageable subsets of slots that are actually relevant to the property being verified. By dividing the memory verification problem into smaller segments, the computational complexity is reduced while maintaining verification effectiveness for the properties of interest.
2Productivity
If designer annotations are used to speed up model checking, then verification time is reduced, but the process becomes time-consuming for the designer
Solution Approach 1:
The patent implements self-service by automatically identifying and abstracting relevant memory slots without requiring designer annotations. The verification tool autonomously analyzes the design and determines which memory slots are relevant to the properties being verified, eliminating the need for manual designer intervention while maintaining verification speed.
3Productivity
If abstractions of the design are computed to speed up verification, then verification efficiency is improved, but the computation becomes as hard as solving the original problem
Solution Approach 1:
The patent applies partial action by computing abstractions only for the specific subset of memory slots that are relevant to the verification property, rather than computing a complete abstraction of the entire design. This partial abstraction approach achieves verification efficiency without incurring the full computational cost of complete design abstraction.
4Measurement precision
If word-level analysis is applied to designs with wide datapaths and large memories, then verification accuracy is improved, but the problem becomes harder to solve
Solution Approach 1:
The patent applies local quality by maintaining word-level analysis precision only for the relevant memory slots and datapath elements that are critical to the verification property. Rather than applying uniform word-level analysis to the entire large memory, the method focuses computational resources on local regions where precision is most needed, reducing overall problem difficulty while maintaining verification accuracy.
Data Source
AI summary
A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist by replacing memory with substitute nodes representing selected slots in the memory, segmenting word level nodes, including one or more of the substitute nodes, in the netlist into segmented nodes, finding reduced safe sizes for the segmented nodes and generating an updated data structure representing the circuit design using the reduced safe sizes of the segmented nodes. The correctness of such systems can require reasoning about a much smaller number of memory entries and using nodes having smaller bit widths than exist in the circuit design. As a result, the computational complexity of the verification problem is substantially reduced.