Netlist Reduction for Memory Verification
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Solution Overview
Problem
Current model checking technologies face difficulties in verifying complex hardware designs with large memories and wide datapaths, as they require time-consuming designer annotations and computationally hard abstractions, and are limited in analyzing sequential systems and properties.
Innovation Solution
A netlist reduction method that abstracts circuit designs with memories into smaller representations, using a directed acyclic graph to reduce memory slots and implement substitute nodes for verification, allowing for efficient checking of properties through a counter-example guided refinement process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional model checking is applied to verify hardware designs with large memories, then verification completeness is improved, but computational complexity and verification time increase significantly
Solution Approach 1:
The patent segments the memory verification problem by introducing word-level abstraction that groups bit-level signals into meaningful data entities. This allows the verification tool to reason about memory at a higher level (words rather than individual bits), reducing the computational complexity while maintaining verification completeness for properties expressed at the word level.
Solution Approach 2:
The patent extracts only the necessary memory information required for verification by using abstraction to identify and focus on specific memory words that are relevant to the property being verified. This extraction approach eliminates unnecessary detail from the verification process, reducing computational complexity while preserving verification completeness for the target properties.
2Measurement precision
If designer annotations are used to guide model checking, then verification accuracy is improved, but time consumption increases
Solution Approach 1:
The patent enables the verification system to automatically generate and refine abstractions without requiring manual annotations from designers. The system self-adjusts by using counter-example guided abstraction refinement, where the tool automatically identifies which memory words need to be tracked based on the verification properties, eliminating the time-consuming manual annotation process while maintaining verification accuracy.
Solution Approach 2:
The patent implements counter-example guided abstraction refinement where the verification system uses feedback from counter-examples to automatically refine the abstraction. This feedback mechanism allows the system to learn which memory words are critical for verification and automatically adjust the abstraction level, achieving verification accuracy without manual designer annotations.
3Productivity
If abstractions are computed to simplify verification, then verification speed is improved, but computational difficulty increases
Solution Approach 1:
The patent applies partial abstraction by tracking only the specific memory words that are necessary for verifying the given properties, rather than creating a complete abstraction of all memory contents. This partial action approach maintains verification speed by focusing computation only on relevant portions of the memory, avoiding the computational hardness of fully abstracting entire large memory structures.
4Reliability
If word-level analysis is performed on designs with large memories, then verification effectiveness is improved, but tool capability requirements increase
Solution Approach 1:
The patent makes the verification tool universally applicable to different memory sizes and configurations by using a general abstraction framework that can handle any memory structure. The word-level abstraction mechanism works consistently across different designs, making the tool versatile without requiring specialized capabilities for each specific memory configuration.
Data Source
AI summary
A computer implemented representation of a circuit design including memory is abstracted to a smaller netlist, which can be analyzed by standard verification tools and by other tools that operate on netlists. The correctness of such systems can require reasoning about a much smaller number of memory entries than exist in the circuit design, and by abstracting such memories to a smaller number of entries, the computational complexity of the verification problem is substantially reduced.