Multi-Clocked Netlist Retiming via Domain Partitioning
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Solution Overview
Problem
Traditional retiming methods for integrated circuit designs face challenges in reducing the number of state-holding elements and combinational-path latency, while also suffering from significant runtime issues, which affect the quality and efficiency of the design process.
Innovation Solution
The proposed method involves partitioning multi-clock netlists into regions with identically clocked registers, identifying compatible clock domains, and combining them to create retiming graphs that are then retimed using a solver, allowing for hybrid domain-based and free-running retiming, which reduces the number of state-holding elements and latency while speeding up the retiming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional retiming methods are used to reduce the number of state-holding elements and combinational-path latency, then design quality improves, but runtime increases significantly
Solution Approach 1:
The patent divides the multi-clock netlist into multiple partitions based on clock domain information, where each partition contains registers with identical clocking. This segmentation allows the retiming algorithm to process smaller, independent sub-problems rather than the entire netlist at once, reducing computational complexity and runtime while maintaining design quality through systematic optimization of each partition.
Solution Approach 2:
The patent introduces a new dimension of clock domain partitioning orthogonal to the traditional retiming optimization. By organizing registers into clock domains before applying retiming algorithms, the solution creates a hierarchical structure that enables both quality improvement through optimized register placement and runtime reduction through divided computation.
2Adaptability or versatility
If the entire netlist is converted to low-level representation for monolithic retiming, then retiming can be performed uniformly, but runtime consumption increases to several hours for very-large netlists
Solution Approach 1:
Instead of applying monolithic retiming to the entire converted netlist, the patent segments the netlist into clock domain partitions after conversion to low-level representation. Each partition is then retimed independently, preserving the uniformity benefits of low-level conversion while avoiding the runtime penalty of processing the complete netlist as a single unit.
3Productivity
If domain-based retiming is performed within each identical-clock-domain partition, then retiming can be performed efficiently, but the ability to achieve global optimization is limited
Solution Approach 1:
The patent combines multiple clock domain partitions into a unified retiming framework where registers at partition boundaries can be jointly optimized. By identifying compatible clock domains and merging them into combined partitions, the solution enables global optimization opportunities that span original partition boundaries while maintaining the efficiency benefits of partitioned processing through the hierarchical structure.
Data Source
AI summary
Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.