IC Netlist Retiming Graph for Flexible Register Relocation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing retiming techniques, such as min-cut and ILP-based methods, face limitations in relocating registers to optimize integrated circuit design, leading to suboptimal register reductions and potential alterations in netlist behavior due to restrictive placement and iterative transformations without synergistic improvements.
Innovation Solution
A min-cut based retiming technique that forms a retiming graph without reverse edges in certain regions, models associative-commutative logic cones as single nodes, and allows for fanin register sharing, enabling more flexible register placement and reducing the number of state-holding elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional retiming algorithms (ILP or min-cut) are used to relocate registers, then register count can be reduced, but run-time increases significantly (minutes to hours for very large netlists)
Solution Approach 1:
The retiming problem is segmented into multiple phases: first performing retiming with relaxed constraints to achieve significant register reduction quickly, then performing constrained retiming only on critical paths to meet timing requirements. This divides the complex optimization into manageable stages, reducing overall run-time while maintaining effectiveness.
Solution Approach 2:
The patent applies partial retiming by focusing computational effort only on critical paths and key regions rather than exhaustively optimizing the entire netlist. This partial action approach achieves sufficient register reduction and timing improvement without the excessive computational cost of complete optimization.
2Loss of time
If min-cut retiming is used to achieve fast register reduction, then run-time is reduced, but the set of possible retimed netlists is limited by restrictive placement constraints
Solution Approach 1:
The patent employs dynamic retiming constraints that adapt during the optimization process. Initially, relaxed constraints allow maximum freedom for register relocation to achieve fast results. As the process progresses and critical paths are identified, constraints are dynamically tightened to meet timing requirements. This dynamic approach maintains versatility early on while ensuring correctness later.
Solution Approach 2:
The retiming process is segmented into unconstrained and constrained phases, allowing the algorithm to explore a broad set of possible retimed netlists initially, then narrow down to valid solutions that meet timing constraints. This segmentation preserves adaptability while maintaining fast execution.
3Adaptability or versatility
If reverse edges are included in the retiming graph to allow flexible register placement, then the set of possible retimed netlists expands, but invalid retimed netlists may be formed altering netlist behavior
Solution Approach 1:
The patent incorporates feedback mechanisms that continuously validate retimed netlists against behavioral equivalence constraints. After each retiming operation, the algorithm checks whether the modified netlist maintains correct functionality and timing characteristics. If violations are detected, the operation is rejected or corrected. This feedback loop ensures reliability while allowing flexible placement.
Solution Approach 2:
The patent introduces intermediary validation checks and constraint propagation mechanisms that act as mediators between the flexible retiming process and the requirement for behavioral equivalence. These intermediaries detect and prevent invalid transformations before they compromise netlist correctness, allowing exploration of diverse retimed netlists while maintaining reliability.
4Quantity of substance
If iterative retiming with combinational logic transformations is applied, then register reductions can be achieved, but the process becomes complex and time-consuming
Solution Approach 1:
The patent performs preliminary retiming operations to achieve significant register reduction before applying complex combinational logic transformations. By establishing a baseline retimed netlist first, the subsequent transformation steps operate on a simplified structure, reducing their complexity and time requirements. This preliminary action approach breaks down the complex iterative process into more manageable stages.
Data Source
AI summary
A technique of min-cut based retiming of a netlist includes forming a min-cut based retiming graph based on a netlist of a circuit design. Forming the min-cut based retiming graph includes refraining from use of reverse edges in at least some regions of the min-cut based retiming graph. The technique further includes computing a min-cut of the circuit design based on the min-cut based retiming graph, where the min-cut crosses at least one graph path multiple times in a particular region of the min-cut based retiming graph. Based on the min-cut, a behaviorally equivalent retimed netlist is then formed, including in the particular region.