Network Acceleration Architecture Asynchronous Hardware Software Decoupling
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Solution Overview
Problem
Existing network acceleration solutions for iSCSI and RDMA are limited by embedded CPU capabilities, leading to high latency and inflexibility in protocol processing, especially with evolving TCP implementations, and struggle to adapt to increasing CPU speed and memory bandwidth.
Innovation Solution
A network acceleration architecture that separates data-intensive operations from protocol control, using a dedicated hardware acceleration engine for fast-path execution and software for protocol processing, allowing asynchronous and independent operation, and preserving flexibility in protocol implementation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded CPUs are used for protocol processing in RNIC, then network acceleration is achieved, but latency increases and adaptability to protocol changes deteriorates
Solution Approach 1:
The patent segments the network processing functions by separating data-intensive operations from protocol control operations. Data processing is handled by a dedicated hardware acceleration engine while protocol control is managed by software, allowing asynchronous and independent operation of both components.
Solution Approach 2:
The patent introduces a loose coupling mechanism between hardware and software components that acts as an intermediary, allowing them to operate independently while maintaining coordination. This loose coupling preserves flexibility in protocol implementation without sacrificing performance.
2Productivity
If multiple embedded CPUs are placed on the data path to handle multiple packets simultaneously, then networking throughput increases, but device complexity and implementation difficulty increase
Solution Approach 1:
The patent merges multiple CPU functions into a single integrated architecture that combines a hardware acceleration engine with software protocol processing. This unified approach achieves high throughput without the complexity of multiple separate CPU implementations.
3Productivity
If embedded CPUs are used for protocol processing, then network acceleration is provided, but adaptability to increasing main CPU speed and memory bandwidth deteriorates
Solution Approach 1:
The patent creates a dynamic system where the hardware acceleration engine can operate independently of main CPU speed, while the software component can adapt to changing protocol requirements and increasing CPU capabilities. This dynamic architecture allows the system to evolve with advancing technology.
4Device complexity
If state machine implementation is used for protocol processing, then device complexity is reduced, but flexibility in protocol processing deteriorates
Solution Approach 1:
The patent segments protocol processing into fixed hardware acceleration functions and flexible software control functions. This segmentation allows the hardware to provide simple, efficient data processing while the software maintains flexibility for protocol adaptations.
Data Source
AI summary
A network acceleration architecture for use with TCP, iSCSI and/or RDMA over TCP, including a hardware acceleration engine adapted for communication with and processing data from a consumer application in a system that supports TCP, iSCSI and RDMA over TCP, a software protocol processor adapted for carrying out TCP implementation, and an asynchronous dual-queue interface for exchanging information between the hardware acceleration engine and the software protocol processor, wherein the hardware acceleration engine and the software protocol processor are adapted to operate asynchronously and independently of one another.