Network Acceleration Architecture Asynchronous Streamer TCE
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Solution Overview
Problem
Existing network acceleration solutions for iSCSI and RDMA are limited by embedded CPU capabilities, leading to high latency and increased costs, and lack flexibility in protocol processing, particularly for TCP, which is essential for adapting to changing network conditions.
Innovation Solution
A network acceleration architecture that separates data-intensive operations from protocol control, using a hardware acceleration engine (Streamer) for fast-path data processing and a software TCP Control Engine (TCE) for protocol processing, allowing asynchronous and independent operation, thus preserving flexibility and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If embedded CPUs are used for protocol processing, then data processing operations can be handled, but latency increases and performance benefits are limited
Solution Approach 1:
The system segments protocol processing into two distinct paths: a fast path handled by hardware acceleration engines for time-critical operations, and a slow path handled by embedded CPUs for complex protocol logic. This segmentation allows latency-sensitive operations to bypass CPU processing entirely, resolving the contradiction between data processing capability and latency.
Solution Approach 2:
Descriptor rings serve as an intermediary data structure between the hardware acceleration engines and embedded CPUs. The descriptors contain pre-computed information that allows hardware engines to process packets without CPU intervention for routine operations, while still enabling CPU involvement when complex protocol processing is required. This intermediary mechanism resolves the latency issue while preserving processing capability.
2Productivity
If multiple CPUs are placed on the data path to handle multiple packets simultaneously, then networking rates increase, but implementation difficulty increases and cost increases
Solution Approach 1:
The system uses descriptor ring copies that can be processed in parallel by multiple hardware acceleration engines simultaneously. Instead of requiring multiple complex CPU systems, the same descriptor data structure is replicated and processed by independent hardware engines, achieving high networking rates through hardware parallelism rather than CPU multiplication, thus reducing implementation complexity and cost.
3Speed
If state machine implementation is used, then hardware acceleration can be achieved, but flexibility in protocol processing is lost
Solution Approach 1:
The system dynamically selects between hardware acceleration and software processing based on the specific protocol processing requirements. The descriptor structure includes fields that indicate whether a packet should be processed by the hardware fast path or passed to the software slow path. This dynamic selection mechanism preserves protocol processing flexibility while maintaining high speed hardware acceleration for appropriate operations, resolving the contradiction between speed and adaptability.
Data Source
AI summary
A method for receiving data in a network acceleration architecture for use with TCP (transport control protocol), iSCSI (Internet Small Computer System Interface) and/or RDMA (Remote Direct Memory Access) over TCP, including providing a hardware acceleration engine, called a streamer, adapted for communication with and processing data from a consumer application in a system that supports TCP, iSCSI and RDMA over TCP, providing a software protocol processor adapted for carrying out TCP implementation, the software control processor being called a TCE (TCP Control Engine), wherein the streamer and the TCE are adapted to operate asynchronously and independently of one another, and transmitting a TCP segment with the streamer.