Hardware Network Accelerator Parallel Routing Lookup
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Solution Overview
Problem
Modern processing systems in automotive applications face challenges in efficiently managing complex IP routing tables, leading to significant time requirements for identifying correct routes, especially in gateway nodes, which can hinder performance in handling bandwidth-intensive automotive applications.
Innovation Solution
A processing system with a hardware network accelerator that includes multiple Ethernet communication interfaces, memories, and a memory controller to store and manage IP routing tables, allowing parallel access and selection of the correct communication interface for packet forwarding based on destination IP addresses and next-hop information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based routing table processing is used in gateway nodes, then the system can handle complex routing tables, but the time required for identifying correct routes increases significantly
Solution Approach 1:
The patent replaces software-based routing table processing with a hardware network accelerator that performs routing lookups using parallel circuitry and content-addressable memory (CAM). This mechanical/electrical substitution dramatically reduces route identification time from software execution speeds to hardware switching speeds, while maintaining the ability to handle complex routing tables through dedicated hardware structures.
Solution Approach 2:
The hardware network accelerator acts as an intermediary between the software routing table and the network interfaces. It contains a routing table search engine that receives packets, performs parallel routing lookups using CAM and associative memory, and returns routing decisions to the network interfaces, thereby mediating between software complexity and hardware speed.
2Productivity
If hardware network accelerator with parallel processing is used, then packet forwarding speed increases, but device complexity increases
Solution Approach 1:
The hardware network accelerator is segmented into distinct functional modules: a routing table search engine with content-addressable memory for lookup operations, a separate packet processing unit, and multiple network interface controllers. This segmentation allows parallel processing of routing lookups and packet forwarding while managing complexity through modular design, where each module has a specific function.
Solution Approach 2:
The hardware network accelerator is designed as a universal platform that can handle multiple network protocols (Ethernet, CAN, LIN), various packet types, and different routing table configurations through a single integrated structure. The routing table search engine uses generic associative memory structures that can be programmed to search different data formats, making the hardware accelerator multi-functional without requiring separate dedicated hardware for each protocol.
Data Source
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AI summary
A processing system with a hardware network accelerator (4) is disclosed. The hardware network accelerator (4) comprises a plurality (NP) of Ethernet communication interfaces (401-40NP), a plurality (NB) of memories (481-48NB) and a further memory (50). Each memory (48) stores records (RTEA) comprising destination IP data (IP_DA, SUBNET) identifying a destination IP address range. The further memory (50) stores further records (RTEB), wherein each record (RTEA) is associated univocally with a respective further record (RTEB) and comprises next-hop data (IP_NH) indicating a next-hop IP address, next-hop enable data (IP_NH) indicating whether a respective destination IP address range may be reached directly or via the respective next-hop IP address, and network port data (DST_PORT) indicating an Ethernet communication interface. Each Ethernet communication interface (40) is configured to obtain an IP packet, access in parallel the memories (48) in order to read the records (RTEA), select a record (RTEA) having a destination IP address range containing the destination IP address of the IP packet, read the further record (RTEB) associated with the selected record (RTEA) from the further memory (50), and select the indicated Ethernet communication interface (40). The selected Ethernet communication interface (40) is configured to transmit an Ethernet frame comprising the IP packet based on the next-hop enable data (IP_NH) and next-hop data (IP_NH). A microprocessor (1020) is adapted (46) to program the records (RTEA) and the further records (RTEB).