Network Adapter Tick Generation for Precise 5G Scheduling

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Solution Overview

Problem

Existing 5G network systems consume excessive CPU resources and power due to the need for continuous monitoring and synchronization threads to generate scheduling ticks, leading to potential delays and inefficiencies in data transmission.

Innovation Solution

Utilizing a network adapter, such as a NIC, to generate scheduling ticks based on precise time information from a radio unit, eliminating the need for dedicated CPU threads and synchronization, and sending interrupts directly to the CPU for scheduling operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If dedicated CPU threads are used to continuously monitor and synchronize radio schedule timeslots, then scheduling accuracy is improved, but CPU resource consumption increases

Engineering Contradiction:
Improvescheduling accuracyVSAvoidCPU resource consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent extracts the tick generation function from the CPU and assigns it to a separate hardware component (timer or dedicated circuit). This allows the CPU to stop running continuous monitoring threads while still receiving accurate timing signals, thereby reducing CPU resource consumption while maintaining scheduling accuracy.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The hardware timer component autonomously generates timing ticks based on the radio schedule without requiring CPU intervention. The system serves itself by having dedicated hardware handle the timekeeping function, freeing the CPU from continuous synchronization tasks.

Inventive Principle:
Principle #25Self-service

2Reliability

If multiple synchronization threads are run to ensure precise timing, then timing reliability is improved, but system complexity increases

Engineering Contradiction:
Improvetiming reliabilityVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the synchronization function from the CPU software layer and implements it in hardware. This single hardware-based solution replaces multiple software threads, maintaining timing reliability while reducing system complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The hardware timer acts as an intermediary between the radio schedule and the CPU. It provides a standardized tick signal that bridges the timing requirements without requiring complex synchronization protocols or multiple threads.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Loss of time

If continuous CPU monitoring is performed to generate scheduling ticks, then scheduling timeliness is improved, but power consumption increases

Engineering Contradiction:
Improvescheduling timelinessVSAvoidpower consumption
Core Design Contradiction:
Loss of timeVSUse of energy by stationary object

Solution Approach 1:

The patent extracts the tick generation function from the power-consuming CPU and assigns it to a low-power hardware timer. The CPU can enter sleep modes between ticks, significantly reducing power consumption while maintaining scheduling timeliness through the hardware's autonomous operation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Instead of continuous monitoring, the system uses periodic tick generation from the hardware timer. The CPU only needs to respond at these periodic intervals rather than continuously monitoring, reducing power consumption while maintaining timely scheduling responses.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12532279B2Scheduling 5G functions using a network adapter
Publication Date: 2026.01.20 MELLANOX TECHNOLOGIES LTD(IL)
  • US12532279B2 patent drawing
  • US12532279B2 patent drawing
  • US12532279B2 patent drawing

AI summary

A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.