Network Adapter Packet Reassembly for Low Latency Multiprocessor Systems
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Solution Overview
Problem
High performance multiprocessor systems face challenges in reducing latency and increasing bandwidth due to limitations in network adapter performance, particularly in packet switching networks, which affect inter-processor communication.
Innovation Solution
A network adapter with an array of downstream packet processors, an upstream packet processor, direct memory access (DMA) engine, packet buffer, and reassembly state machine (RSM) that processes and reassembles out-of-order data packet fragments for efficient transmission and reception, along with physical I/O blocks and plane output queues to optimize packet transmission over a packet switching network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If packets are transmitted sequentially in traditional network adapters, then data integrity is maintained, but transmission latency increases and bandwidth is reduced
Solution Approach 1:
The network adapter performs preliminary actions by pre-assembling packet fragments in the packet buffer before transmission is fully complete. The reassembly state machine prepares fragments in advance and the DMA engine can start transferring data without waiting for the complete packet assembly, enabling early release of packets to reduce latency while maintaining integrity through proper reassembly ordering.
Solution Approach 2:
The patent segments packets into fragments that can be processed and transmitted independently. The reassembly state machine manages these fragments, allowing the DMA engine to transfer individual fragments without waiting for the entire packet, thereby reducing transmission latency and increasing effective bandwidth through parallel processing of packet components.
2Reliability
If network adapters process packets completely before transmission, then data accuracy is ensured, but processing time and system latency increase
Solution Approach 1:
The reassembly state machine performs preliminary reassembly actions by organizing packet fragments in the packet buffer before the actual transmission occurs. This allows the DMA engine to initiate data transfer earlier without compromising accuracy, as fragments are pre-positioned and validated in the correct sequence within the buffer.
Solution Approach 2:
The packet buffer acts as an intermediary between the DMA engine and the transmission interface. It receives fragments in any order from memory, reassembles them in the correct sequence, and then releases them for transmission. This intermediary mechanism ensures data accuracy through proper reassembly while reducing processing time by decoupling fragment reception from transmission completion.
3Productivity
If traditional network adapters use simple packet processing, then device complexity is low, but performance in high-speed networks is insufficient
Solution Approach 1:
The network adapter is segmented into distinct functional modules: DMA engine for memory transfer, reassembly state machine for fragment management, packet buffer for storage and ordering, and physical I/O blocks for transmission. Each module handles specific tasks, enabling high-speed network throughput while keeping individual components manageable and the overall architecture modular.
Solution Approach 2:
The reassembly state machine performs multiple functions: receiving fragments in any order, validating fragment addresses, reassembling fragments in correct sequence, and coordinating with both the DMA engine and physical I/O blocks. This multi-functionality increases productivity without proportionally increasing complexity, as a single component handles multiple critical tasks.
Data Source
AI summary
A high performance network adapter is provided for forwarding traffic and providing adaptation between packetized memory fragment based processor links of multiple CPUs and multiple switch planes of a packet switching network. Low latency for short and long packets is provided by innovative packet reassembly, overlapping transmission, and reverse order transmission in the upstream direction, and cut through operation in the downstream direction.