Network Adapter PCIe Configuration Access via Management Packets

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Solution Overview

Problem

Accessing the PCIe configuration space of network elements, such as switches and servers, is often slow and complex, especially for remote users, as existing methods require complex APIs and operating system support, limiting flexibility and speed.

Innovation Solution

A network adapter with logic circuitry that receives bus configuration request packets, generates and sends bus configuration cycles, and responds to these requests, allowing remote or local access to the PCIe configuration space without CPU intervention, using management packets like InfiniBand MAD or Ethernet E-MAD, and direct connections via I2C bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If existing methods are used to access PCIe configuration space, then access can be achieved through standard interfaces, but the access speed is slow and the process is complex

Engineering Contradiction:
Improveaccess speedVSAvoidaccess complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces a network adapter as an intermediary device that receives configuration requests over the network and translates them into PCIe configuration cycles. This mediator handles the complexity of PCIe access internally, allowing remote users to access configuration space through simple network packets without needing to understand or implement complex PCIe protocols or APIs.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces the traditional mechanical/software-based PCIe access mechanism (requiring CPU intervention, driver loading, and API calls) with a network-based communication mechanism. Configuration requests are transmitted as network packets (such as InfiniBand MAD or Ethernet E-MAD packets) that are processed by the network adapter's logic circuitry, eliminating the need for complex operating system support and enabling faster access.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If remote access to PCIe configuration space is enabled, then flexibility is improved, but access speed decreases

Engineering Contradiction:
Improveaccess flexibilityVSAvoidaccess speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

The patent segments the access path into two independent parts: network communication (handled by the network adapter) and PCIe configuration cycles (handled by the bus interface). This segmentation allows remote access requests to be processed directly by the network adapter without involving the CPU or operating system, maintaining high speed while enabling flexible remote access from any network location.

Inventive Principle:
Principle #1Segmentation

3Speed

If CPU intervention is required for PCIe configuration access, then system control is maintained, but access speed is limited and flexibility is reduced

Engineering Contradiction:
Improveaccess speedVSAvoidautomation level
Core Design Contradiction:
SpeedVSExtent of automation

Solution Approach 1:

The network adapter is designed with self-service capabilities through its logic circuitry, which automatically receives configuration requests over the network, validates them against a set of requirements, generates the appropriate PCIe configuration cycles, and sends responses back over the network. This self-service mechanism eliminates the need for CPU intervention while maintaining system control through programmable validation rules.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10503682B1Accessing PCIe configuration data through network
Publication Date: 2019.12.10 MELLANOX TECHNOLOGIES LTD(IL)
  • US10503682B1 patent drawing
  • US10503682B1 patent drawing
  • US10503682B1 patent drawing

AI summary

A network adapter includes one or more ports for communicating over a communication network, a bus interface, and logic circuitry. The bus interface is configured to communicate over a bus. The logic circuitry is configured to receive bus configuration request packets from an originator, to control the bus interface to generate one or more bus configuration cycles in response to at least some of the bus configuration request packets, and, in response to the bus configuration cycles, to generate and send bus configuration response packets to the originator of the bus configuration request packets.