Network Adapter Time-Aware Packet Processing Pipeline

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Solution Overview

Problem

Existing packet processing techniques in network adapters lack the ability to perform time-aware operations, which are crucial for synchronizing network elements and optimizing packet handling based on network time.

Innovation Solution

A network adapter with packet processing circuitry that receives network time indications and matches packets to rules with conditions and actions dependent on this time, allowing for actions such as controlling packet departure, modifying timestamps, and updating statistical information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If traditional packet processing techniques are used, then the network adapter can handle basic packet forwarding, but it lacks the ability to perform time-aware operations for synchronizing network elements

Engineering Contradiction:
Improvetime-aware packet processing capabilityVSAvoidpacket processing circuitry complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent embeds a hardware clock and timestamping circuit within the packet processing circuitry of the network adapter. The hardware clock provides time indications that are nested into the packet processing pipeline, allowing time-aware operations to be integrated within the existing packet processing architecture without requiring a completely separate synchronization system

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The packet processing circuitry is designed to perform multiple functions: traditional packet steering and forwarding, plus time-aware operations such as matching packets to time-dependent rules, controlling packet departure times, and updating statistical information based on network time. This multi-functional approach adds time-aware capabilities without requiring entirely separate processing paths

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If packet processing operations are made time-aware with network time synchronization, then packet handling efficiency and accuracy are enhanced, but the device requires additional hardware clock and timestamping circuitry

Engineering Contradiction:
Improvepacket handling efficiencyVSAvoidhardware clock and timestamping circuitry
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the hardware clock and timestamping circuitry with the packet processing circuitry into a unified structure. The hardware clock is integrated to provide time indications directly to the packet processing pipeline, and the timestamping circuit is combined with the packet processing stages to insert timestamps without requiring separate external synchronization hardware

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The network adapter performs self-time-stamping by incorporating a timestamping circuit that automatically inserts network time indications into packets at specific processing stages. This eliminates the need for external timestamping hardware or post-processing timestamp addition, as the system stamps packets itself during normal processing operations

Inventive Principle:
Principle #25Self-service

3Reliability

If rules are matched based on network time conditions, then synchronized packet processing across network elements is achieved, but the rule matching complexity increases with time value comparisons and range extensions

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidrule matching logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary time value extensions before rule matching. The packet processing circuitry pre-calculates time ranges by extending first time values (such as arrival times or current network time) into valid time windows before comparing them with second time values in the rules. This preliminary preparation simplifies the actual matching operation by reducing it to a straightforward range comparison rather than complex temporal logic evaluation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11271874B2Network adapter with time-aware packet-processing pipeline
Publication Date: 2022.03.08 MELLANOX TECHNOLOGIES LTD(IL)
  • US11271874B2 patent drawing
  • US11271874B2 patent drawing

AI summary

A network adapter includes a host interface configured to communicate with a host, a network interface configured to communicate with a communication network, and packet processing circuitry. The packet processing circuitry is configured to receive a packet from the host via the host interface, or from the communication network via the network interface, to receive an indication of a network time used for synchronizing network elements in the communication network, to match the packet to a rule, the rule including a condition and an action, and to perform the action in response to the packet meeting the condition, wherein one or more of (i) the condition in the rule and (ii) the action in the rule, depend on the network time.