Network-Attached Memory for Collective Operation Communication

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Solution Overview

Problem

Collective operations in parallel computing systems face challenges due to the large quantity of messages passed between process entities, leading to resource overload and performance issues in computer nodes, particularly in large systems with hundreds or thousands of process entities.

Innovation Solution

Employing network-attached memory allows computer nodes to exchange data through a shared memory region instead of messages, reducing communication quantities and offloading computations to memory servers to alleviate processing resource burdens.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If message passing is used for collective operations, then process entities can communicate data, but the quantity of messages increases to P*(P-1) causing resource overload

Engineering Contradiction:
Improvecommunication efficiencyVSAvoidnumber of messages
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent introduces a shared memory space as an intermediary mechanism between process entities. Instead of direct message passing requiring P*(P-1) communications, process entities write data to shared memory locations and read from them, reducing communication complexity to O(P) operations. The shared memory acts as a mediator that eliminates the need for explicit point-to-point messaging.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent merges multiple communication operations into a single shared memory access pattern. Multiple process entities can simultaneously access and modify shared memory locations through atomic operations, combining what would traditionally require multiple sequential messages into unified memory operations that scale more efficiently.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If collective operations are performed with many process entities, then computational tasks can be distributed, but processing resources become overloaded

Engineering Contradiction:
Improvecomputational throughputVSAvoidprocessing resource capacity
Core Design Contradiction:
ProductivityVSPower

Solution Approach 1:

The patent extracts computation-intensive operations from the CPU-bound process entities and relocates them to GPU-based rendering devices. By taking out heavy computational tasks from the traditional processing pipeline and offloading them to dedicated graphics processors, the system maintains high computational throughput while preventing CPU resource overload.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces traditional CPU-based processing mechanisms with GPU-based parallel processing mechanisms. Instead of using conventional processor instructions for collective operations, the system leverages graphics processing units to execute computation-intensive tasks, substituting a different hardware architecture that provides higher parallel processing capacity.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Ease of operation

If traditional message passing is used, then data exchange between nodes is achieved, but communication overhead increases significantly

Engineering Contradiction:
Improvedata exchange capabilityVSAvoidcommunication overhead
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements preliminary actions by pre-establishing shared memory regions and memory mapping before collective operations begin. Process entities allocate memory segments in advance and set up access permissions, so that during actual data exchange operations, they can directly access pre-configured memory locations without performing complex message routing or allocation operations at runtime.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250021273A1Collective operation using a network-attached memory
Publication Date: 2025.01.16 HEWLETT PACKARD ENTERPRISE DEV LP
  • US20250021273A1 patent drawing
  • US20250021273A1 patent drawing
  • US20250021273A1 patent drawing

AI summary

In some examples, a processor receives a first request to allocate a memory region for a collective operation by process entities in a plurality of computer nodes. In response to the first request, the processor creates a virtual address for the memory region and allocates the memory region in a network-attached memory coupled to the plurality of computer nodes over a network. The processor correlates the virtual address to an address of the memory region in mapping information. The processor identifies the memory region in the network-attached memory by obtaining the address of the memory region from the mapping information using the virtual address in a second request. In response to the second request, the processor performs the collective operation.