Network Bus Framework for Distributed Processing Scalability
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Solution Overview
Problem
Current distributed processing systems face scalability limitations due to bottlenecks in server communication and high development costs, and they struggle to communicate effectively with processorless hardware devices like cameras, which require a method to enable seamless data processing across multiple processor nodes.
Innovation Solution
A network bus framework is established, allowing processor nodes to connect hardware devices via a data network, with a network bus driver and device drivers creating a bus abstraction layer, enabling hot-swappable devices and memory sharing, and using a distributed memory manager for consistent data updates across nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a client/server architecture is used for distributed processing, then resource sharing and communication between processor nodes are enabled, but the server becomes a bottleneck limiting system scalability
Solution Approach 1:
The patent segments the centralized server functionality into distributed bus controllers at each processor node. Instead of one central server handling all communications, each node can independently control bus operations, dividing the communication burden and eliminating the single-point bottleneck that limits scalability.
Solution Approach 2:
The patent makes each processor node potentially capable of serving multiple roles - acting as both a client and a server, and potentially as a bus controller. This multi-functionality allows any node to handle resource sharing and communication tasks, distributing the workload across the entire system rather than concentrating it in a single server.
2Adaptability or versatility
If distributed operating systems with RPC are used to enable direct processor node communication, then scalability is improved, but development costs increase due to system complexity
Solution Approach 1:
The patent introduces a bus abstraction layer as an intermediary between processor nodes and hardware devices. This layer provides standardized interfaces and protocols that simplify development, allowing nodes to communicate through a common bus protocol rather than requiring complex RPC implementations, thereby reducing development costs while maintaining direct communication capabilities.
Solution Approach 2:
The patent changes the communication parameter from high-level RPC calls to lower-level bus controller commands. By operating at the bus controller level rather than the application level, the system achieves direct communication with reduced overhead and simpler implementation, lowering development complexity and cost.
3Ease of manufacture
If processorless hardware devices are deployed for cost-effective data processing, then system cost is reduced, but communication capability with processor nodes is limited
Solution Approach 1:
The patent introduces bus controllers as intermediary devices that bridge processorless hardware devices and processor nodes. The bus controller handles all communication protocols and processing tasks, allowing simple, low-cost hardware devices to participate in the distributed system without requiring their own processors, thus maintaining both cost-effectiveness and communication capability.
Solution Approach 2:
The bus controller provides self-service functionality by autonomously managing communication between processorless devices and the network. It handles data buffering, protocol conversion, and error management without requiring processing power from the connected hardware devices, enabling them to remain simple and cost-effective while maintaining full communication capability.
Data Source
AI summary
A method and system for interconnecting peripherals, processor nodes, and hardware devices to a data network to produce a network bus providing OS functionality for managing hardware devices connected to the network bus involves defining a network bus driver at each of the processor nodes that couples hardware device drivers to a network hardware abstraction layer of the processor node. The network bus can be constructed to account for the hot-swappable nature of the hardware devices using a device monitoring function, and plug and play functionality for adding and, removing device driver instances. The network bus can be used to provide a distributed processing system by defining a shared memory space at each processor node. Distributed memory pages are provided with bus-network-wide unique memory addresses, and a distributed memory manager is added to ensure consistency of the distributed memory pages, and to provide a library of functions for user mode applications.