Network Chip DMA Channels for Shorter Software Update Blackouts
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Solution Overview
Problem
Network devices experience undesirable blackout periods during software updates due to the processing of network traffic being paused, which negatively impacts network performance.
Innovation Solution
Implementing a network device configuration that includes a host processor and a coprocessor to perform direct memory access (DMA) operations, utilizing command coalescing, multiple DMA channels, resource-specific command queues, and dynamic re-allocation of DMA channels to accelerate the writing of network data into data storage resources, thereby minimizing blackout time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written to the network device during software updates, then the network device can receive updates, but the processing of network traffic must be paused creating a blackout time period
Solution Approach 1:
The patent divides the data writing process into multiple parallel DMA channels that can simultaneously write different portions of data to different data storage resources. This segmentation allows the update process to be divided into concurrent operations rather than a single sequential process, reducing the total blackout time while maintaining reliable software updates.
Solution Approach 2:
The host processor coalesces multiple data write commands into a single DMA operation before transferring data to the network device. This preliminary action prepares the data in advance and consolidates transfer operations, allowing the update process to complete faster and reduce the blackout period duration.
2Speed
If multiple DMA channels are allocated to a single data storage resource, then data transfer speed increases, but the complexity of DMA channel management increases
Solution Approach 1:
The coprocessor dynamically allocates and deallocates DMA channels to different data storage resources based on real-time needs. This dynamic management allows the system to optimize data transfer speed by assigning multiple channels to resources requiring high throughput while automatically adjusting to reduce complexity when full parallelism is not needed.
Solution Approach 2:
The system monitors the state of data storage resources and adjusts DMA channel allocation accordingly. This feedback mechanism ensures that multiple DMA channels are allocated to a single data storage resource only when necessary for high-speed transfers, automatically reducing channel management complexity during normal operation while maintaining high speed when needed.
Data Source
AI summary
A data processing system can include a first processor, a second processor, and one or more data storage resources each configured to store data for processing network traffic. The second processor can help the first processor perform direct memory access (DMA) operations to write the data into the one or more data storage resources using DMA channels. DMA channels may be allocated between the data storage resources based on the allocation of data for storage on different data storage resources.