Software Pipelining on Network-on-Chip with Smart Pointer Memory
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Solution Overview
Problem
Current data processing paradigms, such as pure MIMD and pure SIMD, are not optimized for applications that require both parallel processing and fast random access to shared memory, limiting their effectiveness for certain types of real-world simulation programs.
Innovation Solution
A Network on Chip (NOC) architecture that integrates processor blocks, routers, memory communications controllers, and network interface controllers, allowing for shared memory management through smart pointers and flexible software pipelining, enabling efficient inter-IP block communication and memory allocation across stages of a software pipeline.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pure MIMD processing is used, then fast random access to shared memory is provided, but the degree of parallelism is not high
Solution Approach 1:
The software application is segmented into multiple stages of a software pipeline, where each stage executes in a thread of execution on a separate IP block. This segmentation enables parallel execution of multiple stages while maintaining efficient memory access through the shared memory pool accessible by all IP blocks via the NOC.
Solution Approach 2:
The system provides a universal shared memory pool that can be accessed by all IP blocks in the network, enabling both high parallelism through multiple processors and fast random access through a common memory resource. The memory communications controllers enable each IP block to access the shared memory pool efficiently.
2Productivity
If pure SIMD processing is used, then a high degree of parallelism is provided, but fast random access to main memory stores is not provided
Solution Approach 1:
The system dynamically allocates and deallocates shared memory for each stage of the software pipeline using smart pointers. This dynamic memory management allows each processing stage to have efficient access to the memory it needs while maintaining the parallelism benefits of SIMD processing across multiple IP blocks.
Solution Approach 2:
The memory communications controllers act as intermediaries between IP blocks and the shared memory pool, enabling efficient memory access for parallel processing stages. These controllers manage the interface between the processors and memory, providing fast access while supporting high-degree parallelism through the NOC architecture.
3Productivity
If shared memory is allocated for multiple stages, then memory sharing efficiency is improved, but memory management complexity increases
Solution Approach 1:
Each stage of the software pipeline automatically manages its own memory allocation and deallocation through smart pointers. The system provides self-service memory management where stages can allocate memory when needed and deallocate when done, reducing the overall complexity of memory management while improving sharing efficiency through automatic resource cleanup.
Solution Approach 2:
The system uses smart pointers with reference counting to dynamically track memory usage across multiple stages. By changing the memory management approach from static allocation to dynamic reference-based management, the system improves memory sharing efficiency while keeping management complexity tractable through automated tracking.
Data Source
AI summary
Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.