Network Chip Sleep-Frequency Control for Idle Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Network chips in idle states continue to consume high power despite not receiving or sending packets, and existing methods like power off, clock gating, and hard reset affect reliability or are not applicable to all chips.
Innovation Solution
Determine idle network chips based on port, configuration, and traffic status, and control first functional modules to run at a sleep frequency, while ensuring critical modules run at low-power or standard frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If network chips continue to run at standard frequency to ensure functional availability, then reliability is maintained, but power consumption increases significantly
Solution Approach 1:
The patent dynamically adjusts the running frequency of network chips based on their actual workload state. Chips are classified into busy state (running at standard frequency) and idle state (running at sleep frequency), allowing the system to adapt power consumption to actual needs while maintaining functional availability when required.
Solution Approach 2:
The patent changes the operating parameter (running frequency) of network chips from a fixed standard frequency to a variable frequency that can be set to sleep frequency during idle periods. This parameter change enables significant power reduction while maintaining the capability to restore standard frequency when functionality is needed.
2Use of energy by moving object
If clock gating is applied to reduce power consumption, then energy efficiency improves, but reliability is reduced for functional modules manufactured at advanced process nodes
Solution Approach 1:
The patent applies different power management strategies to different functional modules based on their specific characteristics. For functional modules manufactured at advanced process nodes (16nm, 7nm, or more advanced) where clock gating reduces reliability, the patent uses frequency adjustment instead. For other modules, traditional clock gating may still be applied, creating a localized, tailored approach to power management.
Solution Approach 2:
The patent segments functional modules into different categories based on their manufacturing process node and reliability characteristics. This segmentation allows the system to apply appropriate power management techniques to each segment - frequency adjustment for advanced-node modules and clock gating for other modules - thereby optimizing both power consumption and reliability for each segment.
3Use of energy by moving object
If power gating or clock gating is used on functional modules, then power consumption is reduced, but the modules cannot respond timely when needed
Solution Approach 1:
The patent implements periodic monitoring of network chip status to determine when chips transition between busy and idle states. This periodic action enables the system to及时调整 frequency settings, ensuring that chips can be quickly activated from sleep frequency when traffic arrives, reducing the effective wake-up time while maintaining low power consumption during idle periods.
Data Source
AI summary
This disclosure belongs to the field of communication technologies, and provides a network chip management method and apparatus, a communication device, and a storage medium. According to the network chip management method provided in this disclosure, an idle target network chip is determined based on at least one of a port status, a configuration status, and a traffic status of a network chip; and a first functional module in the target network chip is controlled to run at a sleep running frequency, so that power consumption of the target network chip can be effectively reduced.