Multi-Core Network Chip Rerouting for Defect-Tolerant Yield Recovery
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Solution Overview
Problem
Network chips often suffer from defects during fabrication, leading to reduced die yield and limited utility, as defects in multiple cores can render multi-core network chips unusable, hindering efficient data processing and resource utilization.
Innovation Solution
The implementation of multi-core architectures with auxiliary wiring between cores allows for the rerouting of data around defective components, enabling the utilization of functional components from inactive cores, thereby increasing die yield and operational capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-core network chips are fabricated with standard manufacturing processes, then production volume increases, but defect rate increases leading to reduced die yield
Solution Approach 1:
The network chip is divided into multiple independent cores, each capable of being individually tested and activated. This segmentation allows the system to tolerate defects in some cores while maintaining functionality through other healthy cores, thereby improving die yield without sacrificing production volume.
Solution Approach 2:
The system dynamically changes operational parameters by activating or deactivating specific cores based on their functional status. Through configuration bits and control logic, the chip can adapt its operational state to maximize the number of functional cores, effectively converting a fixed-defect scenario into a flexible, optimized configuration that improves overall yield.
2Adaptability or versatility
If auxiliary wiring is added between cores to enable rerouting, then adaptability improves, but device complexity increases
Solution Approach 1:
The auxiliary wiring structure is designed with universal connectivity, where each core can potentially connect to any other core through standardized interconnection paths. This multi-functional wiring approach allows the same physical infrastructure to support multiple rerouting scenarios, reducing the need for dedicated wiring for each possible defect scenario and thereby managing complexity.
Solution Approach 2:
A central control mechanism acts as an intermediary between the defective cores and the auxiliary wiring system. This mediator coordinates the rerouting process, managing the complexity of multiple possible connections by providing a unified control interface that simplifies the overall system architecture while maintaining high adaptability.
3Reliability
If defective cores are completely deactivated, then reliability of individual core operation is maintained, but resource utilization decreases
Solution Approach 1:
The network chip performs self-diagnosis and self-configuration through built-in testing mechanisms. Each core can be automatically tested during fabrication, and the system self-adjusts by activating only the functional cores, eliminating the need for external intervention and maximizing resource utilization while maintaining operational integrity.
Solution Approach 2:
The system transitions from a static configuration where all cores are either fully active or fully deactivated to a dynamic configuration where the operational status of each core can be independently controlled. This dynamic approach allows the system to adapt to manufacturing variations and optimize resource utilization by activating the maximum number of functional cores while maintaining reliability.
Data Source
AI summary
Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer (“SerDes”) block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.