Distributed Network Clock Synchronization With Delay Compensation

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Solution Overview

Problem

Distributed data acquisition networks face challenges in time synchronization due to varying hardware clock frequencies and sample rate errors between nodes, leading to time drift and inadequate precision for temporal alignment in measurements.

Innovation Solution

A distributed network system that includes a master controller with a master clock and modules to account for transmission and receive delays, synchronizing node clocks by modifying the master time with known delays, using deterministic FPGA processing and connection delays to ensure all clocks are aligned with the master clock.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional hardware clocks are used in distributed nodes, then each node can independently maintain its own clock, but time drift and sample rate errors occur between nodes due to varying clock frequencies

Engineering Contradiction:
Improveindependent clock operationVSAvoidtime synchronization precision
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent merges the time reference function across all distributed nodes by establishing a master clock that provides a unified time reference. All slave nodes synchronize their local clocks to the master clock, combining previously independent clock operations into a coordinated system. This is achieved through the master clock generating time references that are distributed to all slave nodes, eliminating time drift between nodes while maintaining independent operation capability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback mechanisms where slave nodes continuously monitor their time synchronization status relative to the master clock and adjust their local clocks accordingly. The system measures time differences between master and slave clocks and applies corrective adjustments to eliminate drift. This closed-loop feedback ensures long-term synchronization precision while allowing nodes to operate independently when synchronization is maintained.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If time synchronization is implemented in distributed networks, then measurement alignment can be achieved, but transmission and receive delays cause synchronization errors

Engineering Contradiction:
Improvemeasurement alignment precisionVSAvoidtransmission and receive delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies preliminary action by measuring and characterizing transmission and receive delays before they affect synchronization accuracy. The system pre-determines the delay values through calibration procedures and uses these predetermined values to compensate for delays in real-time operation. By preparing delay compensation data in advance, the system eliminates synchronization errors caused by transmission delays without adding real-time processing overhead.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the time parameter by applying offset corrections to compensated time references based on measured transmission and receive delays. The system adjusts the time stamps and synchronization signals by adding or subtracting delay values to compensate for transmission time. This parameter transformation converts delayed time references into accurate synchronization signals, maintaining measurement precision despite physical transmission delays.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If deterministic delays are used for synchronization compensation, then precise time alignment can be achieved, but system complexity increases due to multiple delay modules and calibration requirements

Engineering Contradiction:
Improvetime synchronization precisionVSAvoidsynchronization system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements universality by designing the master clock to perform multiple functions: generating time references, measuring transmission delays, and distributing synchronized time to all slave nodes. The slave nodes similarly serve multiple functions by receiving time references, measuring receive delays, and adjusting their local clocks. This multi-functionality reduces the need for separate dedicated components for each synchronization task, simplifying the overall system architecture while maintaining high precision.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Reliability

If all nodes synchronize directly to the master clock, then central control is maintained, but network topology constraints limit scalability

Engineering Contradiction:
Improvecentralized time referenceVSAvoidnetwork topology adaptability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies segmentation by dividing the distributed network into hierarchical levels: master nodes that generate time references and slave nodes that synchronize to them. This segmentation allows the system to scale by adding more master-slave pairs without requiring all nodes to communicate directly with each other. Each segment (master-slave group) maintains independent synchronization while contributing to the overall network time coherence, enabling flexible network topologies including star, mesh, and hierarchical configurations.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11360505B2Distributed network time synchronization
Publication Date: 2022.06.14 SIMMONDS PRECISION PRODUCTS INC
  • US11360505B2 patent drawing
  • US11360505B2 patent drawing

AI summary

A distributed network system can include a master controller having a master clock configured to output a master time, and a master transmission delay time module configured to modify the master time to add a known master transmission delay to the master time to output an adjusted master time. The system can include a first device operatively connected to the master controller and configured to receive the adjusted master time from the master controller.