Network Clock Synchronization Using a Shared Frequency Synthesizer

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Solution Overview

Problem

Current clock synchronization methods in network devices are inflexible and lack accuracy, particularly in scenarios requiring tight synchronization across multiple devices.

Innovation Solution

A communication system with network devices equipped with a frequency synthesizer and control software that adjusts clock signals to iteratively reduce frequency differentials between local and remote clocks, ensuring synchronized clock frequencies across all devices, utilizing a printed circuit board with fan-out circuitry and independent application-specific integrated circuits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If software-based clock synchronization control is used, then ease of operation is improved, but latency and synchronization accuracy deteriorate due to software processing delays

Engineering Contradiction:
Improveease of operationVSAvoidlatency
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent replaces software-based clock synchronization control with a hardware-based frequency synthesizer control system. The frequency synthesizer directly adjusts clock signals in response to frequency differential detections from network devices, eliminating software processing delays and achieving sub-microsecond synchronization accuracy through direct hardware control loops.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If traditional clock synchronization methods are used, then device complexity is reduced, but synchronization accuracy and precision deteriorate

Engineering Contradiction:
Improvesynchronization accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces a frequency synthesizer as an intermediary device between network devices and the clock signal source. This intermediary receives frequency differential information from network devices and generates adjusted clock signals, enabling high-precision synchronization across the network while centralizing the complexity in a dedicated hardware component.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If a single frequency synthesizer serves multiple network devices, then device complexity is reduced, but control signal routing and synchronization management become more complex

Engineering Contradiction:
Improvedevice complexityVSAvoidscalability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The frequency synthesizer is designed with universal functionality to serve multiple network devices simultaneously. It includes multiple output connectors and can generate clock signals for any number of network devices, with the ability to receive control signals from any device in the network, making the system scalable without increasing device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11917045B2Scalable synchronization of network devices
Publication Date: 2024.02.27 MELLANOX TECHNOLOGIES LTD(IL)
  • US11917045B2 patent drawing
  • US11917045B2 patent drawing
  • US11917045B2 patent drawing

AI summary

In one embodiment, a communication system includes network devices, each comprising a network interface to receive at least one data stream, a given network device being configured to recover a remote clock from the at least one data stream received by the given network device, a frequency synthesizer to generate a clock signal and output the clock signal to each of the network devices, wherein the given network device is configured to find a clock frequency differential between the clock signal and the recovered remote clock, and provide a control signal to the frequency synthesizer responsively to the clock frequency differential, the control signal causes the frequency synthesizer to adjust the clock signal so as to iteratively reduce an absolute value of the clock frequency differential between the clock signal and the recovered remote clock.