Automation Network Clock Sequencing for Jitter-Free Time Stamps
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Solution Overview
Problem
In automation communication networks, clock synchronization using integer counter values can lead to deviations in clock increments, causing jitter and incorrect time stamps due to non-integer period durations, which disrupts synchronous data exchange.
Innovation Solution
A method where the internal clock is incremented using a sequence of integer increments defined such that their sum corresponds to an integer multiple of the period duration, minimizing deviations and adapting the clock to the data exchange frequency, thereby eliminating the need for clock domain transformation and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clocks are incremented at the clock frequency, then the data exchange can be synchronized, but the count values deviate from multiples of the period duration causing jitter
Solution Approach 1:
The increment operation is segmented into multiple smaller steps instead of a single large increment. The sequence divides the total increment into intermediate values that are applied sequentially, allowing the clock to pass through intermediate states that minimize deviation from ideal timing points.
Solution Approach 2:
The sequence of increment values is pre-calculated and stored before the clock operation begins. This preliminary preparation allows the system to execute the optimized increment sequence without real-time computation delays, ensuring that timing deviations are minimized from the start of each clock cycle.
2Adaptability or versatility
If clock domain transformation is performed, then the clock frequency can be adapted, but the transformation delay causes time deviation from reference time
Solution Approach 1:
The clock domain transformation function is extracted and implemented directly within the clock incrementing logic itself, rather than as a separate transformation stage. This integration eliminates the need for distinct transformation blocks and their associated delays.
Solution Approach 2:
The frequency adaptation and time stamping functions are merged into a single unified process. The clock increment sequence simultaneously achieves frequency adaptation and generates accurate time stamps, eliminating the sequential execution of separate transformation and timestamping operations.
Data Source
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AI summary
A network participant (7) of an automation communication network (1) is provided in order to exchange data with additional network participants (2) in the automation communication network (1) at a defined clock frequency. The network participant (7) has an internal clock (8) for synchronizing the data exchange with at least one additional network participant (7). The internal clock (8) is provided in order to provide a time as an integer count value. The clock frequency is defined such that a period duration per cycle of the internal clock (8) cannot be represented by an integer count value. A method for operating the network participant (7) in the automation communication network (1) comprises the following method step: The internal clock (8) is incremented by means of a defined sequence of integer increments. The sequence of integer increments is defined such that a sum of the integer increments corresponds to an integer multiple of the period duration.