Network Clock Synchronization Using On-Chip PLL Feedback
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Solution Overview
Problem
Conventional network synchronization methods rely on external circuitry for generating synchronized clock signals, which can be costly and less scalable, and do not efficiently compensate for frequency drifts or changes in network clock frequencies.
Innovation Solution
A network device with a packet processor, interface circuits, a phase-locked loop (PLL) circuit, and a configuration controller that forms a closed loop control system to recover and align the interface clock with the network clock, using existing on-chip components and software to detect and adjust frequency deviations, enabling internal generation and management of synchronized clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external circuitry (dedicated telco PLL) is used to generate synchronized clock signals, then clock signal generation reliability is improved, but device complexity and cost increase
Solution Approach 1:
The patent combines the clock generation function with existing on-chip PLL circuits that are already present for other purposes (such as cleaning jitter). By merging the synchronization function with existing hardware, the patent eliminates the need for separate external telco PLL circuits while maintaining reliable clock signal generation.
Solution Approach 2:
The patent makes existing on-chip PLL circuits multi-functional by using them both for their original purpose (jitter cleaning) and for synchronization. The same PLL hardware is configured differently to perform clock generation for synchronization, eliminating the need for dedicated external synchronization circuitry.
2Measurement precision
If external telco PLL is used for synchronization, then clock signal accuracy is maintained, but scalability and adaptability deteriorate
Solution Approach 1:
The patent enables network devices to generate their own synchronized clock signals using internal PLL circuits configured through software/firmware. Each device independently recovers and tracks the network clock frequency without requiring external synchronization hardware, making the system self-sufficient and highly scalable.
Solution Approach 2:
The patent changes the operational parameters of existing PLL circuits through software configuration rather than requiring dedicated hardware. By dynamically adjusting PLL parameters (such as frequency division ratios) based on recovered network clock frequency, the system achieves accurate synchronization while maintaining adaptability to different network conditions and device types.
3Device complexity
If conventional synchronization methods are used, then implementation simplicity is maintained, but ability to compensate for frequency drift deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the device continuously monitors the recovered network clock frequency, compares it with the internal system clock, and dynamically adjusts the PLL configuration to compensate for frequency drift. This closed-loop control ensures accurate synchronization despite variations in network clock frequency over time.
Solution Approach 2:
The patent transitions from static synchronization (fixed external PLL configuration) to dynamic synchronization where the PLL parameters are continuously adjusted based on real-time frequency measurements. The system adapts its operation to track network clock frequency changes, providing robust compensation for drift while maintaining implementation simplicity through software control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for high scalability and accuracy in network synchronization, maintaining synchrony across nodes with minimal external dependencies and effectively compensating for frequency drifts, achieving clock accuracy of 0.01 parts per billion over a year.
Implementation Method 1
The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit
Data Source
AI summary
A network device includes a packet processor, a plurality of interface circuits, a phase-locked loop (PLL) circuit and a configuration controller. The interface circuits are configured to transmit and receive signals to/from other devices that are coupled to the network device. A master interface circuit among the interface circuits is configured to recover a network clock from a received signal. The PLL circuit is configured to generate an interface clock based on a system clock of the network device and a configuration of the PLL circuit and to provide the interface clock to the plurality of interface circuits to govern communication timings of the interface circuits. The configuration controller is configured to detect a difference of the interface clock relative to the recovered network clock, and to determine the configuration of the PLL circuit based on the difference to govern operation of the PLL circuit.