Network Apparatus Clock Synchronization Using True Offset
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Solution Overview
Problem
Network apparatuses face instability and unreliability in clock synchronization due to fluctuations in network conditions, leading to large deviations in system clock synchronization when relying solely on a first clock offset from a slave port.
Innovation Solution
Determining a true clock offset by combining the first clock offset from a slave port with at least one second clock offset from passive ports, using a clock offset selection algorithm to ensure accurate synchronization, thereby improving stability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the network apparatus synchronizes the system clock based solely on the first clock offset from the slave port, then the synchronization process is simple, but the stability and reliability of clock synchronization deteriorate due to network condition fluctuations
Solution Approach 1:
The patent combines multiple clock offset measurements (first clock offset from slave port and second clock offsets from passive ports) to determine a true clock offset. This merging of multiple measurement sources improves the reliability of clock synchronization by compensating for network condition fluctuations that would affect any single measurement alone.
Solution Approach 2:
The patent introduces passive ports as intermediary measurement channels to obtain second clock offsets. These passive ports serve as additional reference points that help determine the true clock offset without being the primary synchronization source, thereby improving reliability without significantly increasing system complexity.
2Ease of operation
If the network apparatus uses only the first clock offset for synchronization, then the synchronization method is straightforward, but the measurement precision of the clock offset deteriorates due to network fluctuations
Solution Approach 1:
The patent merges multiple clock offset measurements from different ports to determine the true clock offset. By combining the first clock offset from the slave port with second clock offsets from passive ports, the system achieves higher measurement precision that is resistant to network condition fluctuations.
Solution Approach 2:
The patent changes the approach from using a single clock offset parameter to using multiple clock offset parameters (first and second clock offsets) to determine the true clock offset. This parameter change enables the system to compensate for measurement errors caused by network fluctuations.
3Device complexity
If the network apparatus determines clock offset from a single slave port, then the system configuration is simple, but the stability of clock synchronization deteriorates when network conditions fluctuate
Solution Approach 1:
The patent combines clock offset measurements from multiple ports (slave port and passive ports) to determine the true clock offset. This merging provides multiple measurement paths that stabilize the synchronization against network condition changes without requiring complex system reconfiguration.
Solution Approach 2:
The patent makes the passive ports serve multiple functions: they are used for obtaining second clock offsets to improve synchronization stability, while still maintaining their original monitoring functions. This multi-functionality increases stability without significantly increasing system configuration complexity.
Data Source
AI summary
A network apparatus connected with a first clock source and at least one second clock source is provided. The network apparatus includes a system clock, a slave port connected to the first clock source, at least one passive port connected to the at least one second clock source, and a processor that controls synchronization of the system clock. The processor determines, from the slave port, a first clock offset between the system clock and a clock of the first clock source. The processor determines, from the at least one passive port, at least one second clock offset between the system clock and at least one clock of the at least one second clock source. The processor determines a true clock offset based on the first clock offset and the at least one second clock offset and synchronizes the system clock using the true clock offset.