Network Control Apparatus for SoC Bus Architecture Optimization
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Solution Overview
Problem
The existing Bus architecture in System-on-Chip (SoC) technologies faces limitations in connecting multiple intellectual properties (IPs) due to high power consumption, large space requirements, and complex voltage switching, especially with the Advanced Extensible Interface (AXI) Bus, which separates address and data paths, making it difficult to optimize data transmission/reception performance.
Innovation Solution
A network control apparatus and method that supports multiple outstanding address functions without increasing the number of gates, using content addressable memory and packet decoders to manage addresses and data, and arbitters to combine and transmit packets efficiently, optimizing data transmission/reception performance by selecting suitable architectures based on master IP features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If AXI Bus architecture is used to connect IPs, then data transmission performance is improved, but space requirement and power consumption increase due to separate address and data paths
Solution Approach 1:
The patent merges the address path and data path into a single unified bus structure. Instead of having separate physical paths for addresses and data as in traditional AXI Bus, this invention combines them into one shared bus that carries both address and data signals, thereby reducing the overall space requirement while maintaining transmission performance
Solution Approach 2:
The unified bus structure serves multiple functions simultaneously - it carries both address information and data information through the same physical pathway. This multi-functional design eliminates the need for separate dedicated paths, reducing hardware complexity and space consumption while preserving the performance benefits of structured data transmission
2Productivity
If AXI Bus architecture is used to connect IPs, then data transmission performance is improved, but power consumption increases due to voltage switching in separate address and data paths
Solution Approach 1:
By merging address and data paths into a single unified bus, the invention reduces the total number of signal lines that require voltage switching. This consolidation directly reduces the cumulative power consumption associated with driving multiple separate paths, while the unified structure maintains efficient data transmission through coordinated address and data signal delivery
3Ease of operation
If Bus architecture is used to connect IPs, then connection simplicity is maintained, but functionality is limited when multiple IPs need to use the Bus simultaneously
Solution Approach 1:
The patent introduces dynamic arbitration mechanisms that enable multiple IPs to share the unified bus dynamically. Instead of static exclusive access, the bus incorporates arbitration logic that dynamically assigns access rights to different IPs based on their transmission needs, allowing multiple IPs to operate simultaneously with proper conflict resolution
Solution Approach 2:
The unified bus structure acts as an intermediary that coordinates communication between multiple IPs. By serving as a shared medium with integrated arbitration capabilities, the bus mediates between different IP masters and slaves, enabling complex multi-IP scenarios while maintaining the simplicity of a single unified connection structure
Data Source
AI summary
A network control apparatus and network control method is provided. The network control apparatus including: a content addressable memory receiving to store a plurality of addresses which are generated by at least one master intellectual property, determining whether data corresponding to each of the plurality of stored addresses is received, and generating a determination signal; and a packet decoder transmitting each of the plurality of stored addresses and the data corresponding to each of the plurality of stored addresses to a slave intellectual property according to the determination signal. Accordingly, a multiple address issue function can be supported.