Network Controller Packet Counting for Lower Interrupt Load
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Solution Overview
Problem
Current network controllers cause a significant increase in processor load due to frequent interrupt signals when network speed is insufficient, leading to degraded system performance.
Innovation Solution
Implement a network controller with a data check circuit and interrupt controller circuit that count packets to generate interrupt signals only when predetermined count values are met, delaying the interrupt mechanism to reduce processor load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the network controller notifies the main processor for every packet transmission status, then the processor can respond timely to buffer status changes, but the processor load increases significantly due to frequent interrupts
Solution Approach 1:
The patent combines multiple packet transmission status notifications into a single interrupt signal. The interrupt controller circuit accumulates transmission status information from multiple packets and generates one consolidated interrupt signal when a predetermined number of packets are successfully transmitted, rather than generating separate interrupts for each packet. This merging approach maintains buffer management reliability while significantly reducing processor load.
Solution Approach 2:
The patent implements periodic interrupt signaling based on packet count thresholds. The interrupt controller circuit periodically generates interrupt signals at predetermined intervals (when a specific number of packets are successfully transmitted), creating a rhythmic, predictable interrupt pattern. This periodic action reduces the frequency of processor interrupts while ensuring timely buffer management, directly addressing the contradiction between reliability and processor load.
2Measurement precision
If the network controller uses frequent interrupt signals to notify packet transmission status, then the buffer status can be monitored continuously, but the system performance degrades due to increased processor load
Solution Approach 1:
The patent merges multiple buffer status monitoring events into consolidated interrupt signals. Instead of monitoring and interrupting for each individual packet transmission, the interrupt controller circuit combines status information from multiple packets and generates unified interrupt signals. This merging maintains adequate buffer status monitoring precision while improving overall system performance by reducing interrupt overhead.
Solution Approach 2:
The patent applies partial monitoring action by selecting predetermined packet count thresholds for interrupt generation. Rather than monitoring every single packet transmission, the system monitors at strategic intervals (when predetermined numbers of packets are transmitted). This partial monitoring approach maintains sufficient buffer status awareness while reducing the excessive action of continuous monitoring, thereby improving system performance.
Data Source
AI summary
A network controller includes a data check circuit and an interrupt controller circuit. The data check circuit verifies whether multiple packets are valid. The interrupt controller circuit counts according to a first packet in the multiple packets when the first packet is valid to generate a first count value, and issues an interrupt signal to a processor when the first count is equal to a first predetermined value.