Network Device Packet Processing Latency Reduction

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Solution Overview

Problem

Existing computing systems face challenges in reducing packet processing latency due to the high number of transactions on the PCI-based bus and the need for notifications from the host processor to initiate packet processing.

Innovation Solution

Implementing detection logic at the network device to detect when data has been written to the packet header and descriptor queues, allowing the network device to begin processing packets without waiting for notifications from the host processor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the network device waits for notifications from the host processor to initiate packet processing, then the system maintains simple control logic and ensures data readiness, but packet processing latency increases

Engineering Contradiction:

Improvepacket processing latencyVSAvoidcontrol logic complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The detection logic continuously monitors the packet header queue and packet descriptor queue to detect when data has been written, enabling the network device to initiate packet processing immediately without waiting for host processor notifications. This preliminary detection action eliminates the notification waiting time and reduces packet processing latency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The network device performs self-detection of data availability through its own detection logic, rather than relying on external notifications from the host processor. This self-service mechanism allows the network device to autonomously determine when packets are ready for processing, reducing dependency on host processor actions and minimizing latency

Inventive Principle:

Principle #25Self-service

2Loss of time

If the host processor sends frequent notifications to the network device to initiate packet processing, then packet processing latency is reduced, but the number of PCI bus transactions increases

Engineering Contradiction:

Improvepacket processing latencyVSAvoidPCI bus transactions

Core Design Contradiction:

Loss of timeVSQuantity of substance

Solution Approach 1:

The notification function is extracted from the host processor and implemented as integrated detection logic within the network device. This extraction eliminates the need for repeated PCI bus transactions between the host processor and network device, as the detection and processing initiation now occur locally within the network device

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The detection logic acts as an intermediary mechanism that bridges the gap between data writing and packet processing initiation. Instead of requiring direct host processor notifications, the detection logic autonomously monitors queue status and triggers processing when appropriate, reducing the frequency of host-device communication transactions

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12321301B1Low-latency packet processing for network device

Publication Date: 2025.06.03 AMAZON TECH INC

AI summary

Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.